HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
Granted: June 24, 2010
Application Number:
20100155817
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level…
MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
Granted: June 10, 2010
Application Number:
20100142269
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide…
DETERMINISTIC-BASED PROGRAMMING IN MEMORY
Granted: June 10, 2010
Application Number:
20100142284
Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective…
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
Granted: June 3, 2010
Application Number:
20100133605
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing…
MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY
Granted: June 3, 2010
Application Number:
20100135082
Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level,…
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB
Granted: May 27, 2010
Application Number:
20100128521
Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify…
MULTI-PHASE PROGRAMMING OF MULTI-LEVEL MEMORY
Granted: May 27, 2010
Application Number:
20100128524
Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed…
SPI ADDRESSING BEYOND 24-BITS
Granted: May 27, 2010
Application Number:
20100131676
A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of unused binary values under the conventional SPI command protocol. A number of address bytes required to access the storage location for the command are mapped on a second nibble, and a user and/or system definable number of…
ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT
Granted: May 20, 2010
Application Number:
20100122908
An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in…
ERROR CORRECTION FOR FLASH MEMORY
Granted: May 13, 2010
Application Number:
20100122146
Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error…
MEMORY DEVICE ETCH METHODS
Granted: May 13, 2010
Application Number:
20100120239
A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane…
FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
Granted: May 6, 2010
Application Number:
20100109070
A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
Apparatus and Method for Placement of Boosting Cell With Adaptive Booster Scheme
Granted: May 6, 2010
Application Number:
20100110819
A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost…
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
Granted: April 29, 2010
Application Number:
20100103732
A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and…
APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY
Granted: April 22, 2010
Application Number:
20100097876
A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The…
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
Granted: April 22, 2010
Application Number:
20100099249
Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions…
HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
Granted: March 25, 2010
Application Number:
20100074004
Flash memory systems and methodologies are provided herein for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash…
EEPROM EMULATION IN FLASH DEVICE
Granted: March 25, 2010
Application Number:
20100074005
Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase…
DYNAMIC ERASE STATE IN FLASH DEVICE
Granted: March 25, 2010
Application Number:
20100074006
Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell…
FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
Granted: March 25, 2010
Application Number:
20100074007
Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies.…
