QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
Granted: March 25, 2010
Application Number:
20100074009
Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase entity is a combination of neighboring drain/source regions of two adjacent physical memory cells. By mapping two adjacent physical cells as a single logical cell, the flash memory…
SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES
Granted: March 25, 2010
Application Number:
20100074008
Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity…
HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES
Granted: March 11, 2010
Application Number:
20100059762
Described are Silicon-on-Insulator devices containing a diamond-like carbon layer, methods of making the Silicon-on-Insulator devices, and methods of using the Silicon-on-Insulator devices.
IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING
Granted: March 4, 2010
Application Number:
20100058151
Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.
PROCESS OF FABRICATING A WORKPIECE USING A TEST MASK
Granted: March 4, 2010
Application Number:
20100055809
A product workpiece can be processed to form product dice. A test mask can allow intentional changes to be made to a feature on the product workpiece to examine how the altered feature performs. Use of the test mask may be used or not used based on the needs or desires of skilled artisans. By using the test mask, a separate dedicated test structure is not required to be formed in a scribe lane or within an area that could otherwise be used for a product die. Thus, the sampling level by…
Multi-Level Storage Algorithm To Emphasize Disturb Conditions
Granted: February 11, 2010
Application Number:
20100037032
Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages,…
THERMOELECTRIC DEVICE FOR USE WITH STIRLING ENGINE
Granted: January 28, 2010
Application Number:
20100018202
An exhaust gas manifold having thermoelectric devices in the exhaust manifold of a stirling engine is disclosed.
PROBE APPARATUS, A PROCESS OF FORMING A PROBE HEAD, AND A PROCESS OF FORMING AN ELECTRONIC DEVICE
Granted: January 21, 2010
Application Number:
20100013504
A probing apparatus includes a set of conductors configured to contact a surface of a workpiece simultaneously. A processor activates subsets of the conductors to determine a four-point-probe parameter, wherein the subset is less than the set of conductors. Another subset determines another four-point-probe parameter. The set of conductors remain in contact with the surface of the workpiece during and between activating each subset. A process of forming a probe head includes a probe…
READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS
Granted: December 24, 2009
Application Number:
20090316481
Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one…
IMAGING DEVICE
Granted: December 10, 2009
Application Number:
20090302203
An imaging device suitable for detecting certain imaging particles and recording the detection of imaging particles, and as such can include certain recording devices such as a charge storage structure.
MEMORY DEVICE AND METHOD
Granted: December 10, 2009
Application Number:
20090303798
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a…
MEMORY DEVICE AND METHOD
Granted: December 10, 2009
Application Number:
20090303795
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a…
MEMORY DEVICE AND METHOD
Granted: December 10, 2009
Application Number:
20090303793
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a…
ADDRESS CACHING STORED TRANSLATION
Granted: December 3, 2009
Application Number:
20090300318
Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined…
INSTANT HARDWARE ERASE FOR CONTENT RESET AND PSEUDO-RANDOM NUMBER GENERATION
Granted: December 3, 2009
Application Number:
20090300312
Systems and methods that facilitate securing data associated with a memory from security breaches are presented. A memory component includes nonvolatile memory, and a secure memory component (e.g., volatile memory) used to store information such as secret information related to secret processes or functions (e.g., cryptographic functions). A security component detects security-related events, such as security breaches or completion of security processes or functions, associated with the…
BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF
Granted: November 5, 2009
Application Number:
20090273998
A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase,…
OPTICAL ERASE MEMORY STRUCTURE
Granted: October 22, 2009
Application Number:
20090261367
A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE
Granted: October 15, 2009
Application Number:
20090256242
A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein…
BITLINE VOLTAGE DRIVER
Granted: October 1, 2009
Application Number:
20090244989
A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal,…
FUEL CELL CATALYST REGENERATION
Granted: October 1, 2009
Application Number:
20090246584
Systems and methods that facilitate operating proton exchange membrane (PEM) fuel cells are provided. The methods can involve contacting a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma with a cathode catalyst of a proton exchange membrane fuel cell to reduce the cathode catalyst. The systems employ a fuel supply component that supplies fuel to the proton exchange membrane fuel cell; and a regeneration component that provides a reducing agent…
