FLASH MEMORY USABILITY ENHANCEMENTS IN MAIN MEMORY APPLICATION
Granted: October 1, 2009
Application Number:
20090248958
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
FLASH MEMORY AND OPERATING SYSTEM KERNEL
Granted: October 1, 2009
Application Number:
20090248959
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
SECURE MANAGEMENT OF MEMORY REGIONS IN A MEMORY
Granted: October 1, 2009
Application Number:
20090249014
Systems and/or methods that facilitate controlling access to memory regions in a memory component(s) are presented. A memory component can comprise an access management component that can facilitate controlling access to memory regions that can be respectively associated with authentication credentials. The access control component can facilitate access of a memory region when received authentication information matches authentication information contained in a security record associated…
OPERATING SYSTEM BASED DRAM / FLASH MANAGEMENT SCHEME
Granted: October 1, 2009
Application Number:
20090249015
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL
Granted: October 1, 2009
Application Number:
20090248957
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
WIRELESS MASS STORAGE FLASH MEMORY
Granted: September 24, 2009
Application Number:
20090239468
Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless…
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
Granted: September 17, 2009
Application Number:
20090233422
Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive…
USING LPDDR1 BUS AS TRANSPORT LAYER TO COMMUNICATE TO FLASH
Granted: September 17, 2009
Application Number:
20090235012
One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands…
MEMORY DEVICE AND CHIP SET PROCESSOR PAIRING
Granted: September 3, 2009
Application Number:
20090222910
Systems, devices and/or methods that facilitate mutual authentication for processor and memory pairing are presented. A processor and a suitably equipped memory can be provided with a shared secret to facilitate mutual authentication. In addition, the memory can be configured to verify that the system operating instructions have not been subjected to unauthorized alterations. System integrity can be ensured according to the disclosed subject matter by mutual authentication of the…
SECURE DATA TRANSFER AFTER AUTHENTICATION BETWEEN MEMORY AND A REQUESTER
Granted: August 27, 2009
Application Number:
20090217058
Systems and/or methods are presented that can facilitate controlling access to secure memory blocks within a memory module. The subject innovation can employ key components that can contain two or more storage locations for authentication information that can facilitate controlling access to secure memory block components. Secure memory block counter components can be employed to indicate which storage location within the key component contains current authentication information…
DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES
Granted: August 20, 2009
Application Number:
20090206386
One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance…
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS
Granted: August 20, 2009
Application Number:
20090209107
A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include…
MEMORY DEVICE AND METHOD THEREOF
Granted: August 13, 2009
Application Number:
20090201724
A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at a sense node of a sense amplifier.
EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM
Granted: August 6, 2009
Application Number:
20090198871
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
HARDWARE BASED WEAR LEVELING MECHANISM
Granted: August 6, 2009
Application Number:
20090198872
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
PARTIAL ALLOCATE PAGING MECHANISM
Granted: August 6, 2009
Application Number:
20090198873
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION
Granted: August 6, 2009
Application Number:
20090198874
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES AND A PROCESS OF FORMING THE SAME
Granted: July 30, 2009
Application Number:
20090189202
An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include…
ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM
Granted: July 30, 2009
Application Number:
20090189212
An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom.
TRANSLATION TABLE COHERENCY MECAHANISM USING CACHE WAY AND SET INDEX WRITE BUFFERS
Granted: July 30, 2009
Application Number:
20090193193
Systems and/or methods are presented that provide for recording transactions that occur during a write process in an organized, self-aggregated manner for the purpose of recovering the transactions in the event of a power loss. By implementing an organization that reflects the cache architecture that is organized according to the cache way and set index of each transaction, the amount of time and effort required to recover the modified data from a sudden loss of power event is minimized.…
