RANDOM NUMBER GENERATION THROUGH USE OF MEMORY CELL ACTIVITY
Granted: June 25, 2009
Application Number:
20090165086
Systems and/or methods that facilitate security of data are presented. A random number generation component generates random numbers based in part on electron activity in a select memory cell(s) to facilitate data security. Sensor components that are highly sensitive can be employed to sense activity of the select memory cell(s) and/or reference memory cell in a noise margin associated with respective memory cells in the memory component. The activity of the select memory cell is…
HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE
Granted: June 18, 2009
Application Number:
20090152617
Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher…
POWER SAFE TRANSLATION TABLE OPERATION IN FLASH MEMORY
Granted: June 18, 2009
Application Number:
20090158085
Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be…
ADAPTIVE SYSTEM BOOT ACCELERATOR FOR COMPUTING SYSTEMS
Granted: June 18, 2009
Application Number:
20090158023
An acceleration mechanism for boot-up processing in a computing system is provided. The acceleration mechanism relies on recording most, if not all, of the read transactions, associated with requests and retrievals made during a boot-up and, in some aspects most, if not all, of the write transactions, associated with requests and stores made during a shutdown process. Prior to executing the boot-up process, data associated with the transactions is pre-fetched based on the recorded…
CLOCK ENCODED PRE-FETCH TO ACCESS MEMORY DATA IN CLUSTERING NETWORK ENVIRONMENT
Granted: June 18, 2009
Application Number:
20090158005
Systems and/or methods that facilitate reading data from a memory component associated with a network are presented. A pre-fetch generation component generates a pre-fetch request based in part on a received read command. To facilitate a reduction in latency associated with transmitting the read command via an interconnect network component to which the memory component is connected, the pre-fetch request is transmitted directly to the memory component bypassing a portion of the…
INTELLIGENT MEMORY DATA MANAGEMENT
Granted: June 18, 2009
Application Number:
20090157948
Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management component can perform file management to allocate placement of data and data tags to the memory or to erase data from the memory. Allocation and erasure are based in part on the characteristics of the data tags, and can follow…
HIGH K STACK FOR NON-VOLATILE MEMORY
Granted: June 18, 2009
Application Number:
20090155992
A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of…
METHODS OF FORMING ELECTRONIC DEVICES BY ION IMPLANTING
Granted: June 18, 2009
Application Number:
20090155726
A method of forming an electronic device is provided that includes forming a resist layer over a substrate having a first region, a second region, and a third region. The method further includes directing radiation through a reticle, wherein the reticle comprises different radiation zones having significantly different transmission values with respect to each other, and the first region is exposed to a significantly different amount of radiation as compared to the second region. The…
REFERENCE-FREE SAMPLED SENSING
Granted: June 18, 2009
Application Number:
20090154261
Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a…
SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS
Granted: June 18, 2009
Application Number:
20090154260
Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the…
ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT
Granted: June 18, 2009
Application Number:
20090154251
Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with…
PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
Granted: June 18, 2009
Application Number:
20090154246
Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage…
REDUCED STATE QUADBIT
Granted: June 18, 2009
Application Number:
20090154235
A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one…
READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS
Granted: June 18, 2009
Application Number:
20090154234
Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one…
REDUCING NOISE AND DISTURBANCE BETWEEN MEMORY STORAGE ELEMENTS USING ANGLED WORDLINES
Granted: June 18, 2009
Application Number:
20090154215
Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at…
SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT
Granted: June 18, 2009
Application Number:
20090152669
Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and…
WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTIPLE CHARGE STORAGE ELEMENTS IN AN UNDERCUT REGION
Granted: June 11, 2009
Application Number:
20090146201
A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the…
FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY
Granted: June 11, 2009
Application Number:
20090147585
Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing…
CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE
Granted: June 11, 2009
Application Number:
20090147587
Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.
Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory
Granted: June 11, 2009
Application Number:
20090147589
A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of…
