MEMORY ARRAY SEARCH ENGINE
Granted: June 11, 2009
Application Number:
20090150646
Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory…
WEAVABLE FIBER PHOTOVOLTAIC COLLECTORS
Granted: June 4, 2009
Application Number:
20090139572
Photovoltaic fibers and methods of making photovoltaic fibers are provided. The photovoltaic fiber contains a core, bottom metal-semiconductor compounds over the core, a semiconductor layer comprising semiconductor elements and insulating materials over the bottom metal-semiconductor compounds, and upper metal-semiconductor compounds over the semiconductor layer. The photovoltaic fiber can be weavable. Fabrics including the photovoltaic fibers can be utilized in any suitable application…
FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE
Granted: June 4, 2009
Application Number:
20090140325
A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and…
Method of operating a processing chamber used in forming electronic devices
Granted: June 4, 2009
Application Number:
20090142473
Provided herein is a method of processing an electronic device including operating a processing chamber at a first temperature while a workpiece is being processed and removing the workpiece and a carrier holding the workpiece from the processing chamber while decreasing the temperature within the processing chamber to a second temperature significantly lower than the first temperature. The method also includes increasing the temperature within the processing chamber to a third…
DATA TRANSMISSION SYSTEM-ON-CHIP MEMORY MODEL BASED VALIDATION
Granted: June 4, 2009
Application Number:
20090144045
Systems and/or methods that facilitate simulation, verification, and optimization of a data transmission system by utilizing simulation memory component(s) are presented. A simulation memory component can be used to replace memory components and/or hardware components to facilitate early simulation and/or verification of the overall interconnectivity of the system. A simulation memory component(s) can be configured to emulate various sizes of memory components associated with the system.…
DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
Granted: June 4, 2009
Application Number:
20090144486
Conventional processor and memory configurations place holes into silicon or use expensive multi-layer-laminates/substrates to connect the processor with memory. Using a direct contact between the memory and processor allows for signaling between the two units. By judicious arrangement of the contact areas as well as employing other structures such as carriers and redistributors, adequate power and ground supply can be maintained for the processor. Therefore, there is little-to-no damage…
ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
Granted: May 28, 2009
Application Number:
20090135659
Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of…
MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS
Granted: May 28, 2009
Application Number:
20090138628
Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a…
HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY
Granted: May 21, 2009
Application Number:
20090129172
Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
Granted: May 14, 2009
Application Number:
20090121361
A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12, a second metal 16 provided in the resin 12 over the first metal 14, and being exposed on an upper surface of the resin 12, and a first wire 18 coupling the first semiconductor chip 10 to the first metal 14 and the second metal 16. The first wire 18 is coupled…
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING A CONDUCTIVE LAYER OVER A SEED LAYER
Granted: May 7, 2009
Application Number:
20090114542
A process of forming an electronic device can include placing a seed layer into an electroplating solution within an electroplating tool. The electroplating tool can include a first electrode and a second electrode, wherein the first electrode is electrically connected to the seed layer. The process can also include depositing a first portion of a conductive layer using a first signal of a first type (e.g., direct current) between the first electrode and a second electrode, and…
CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY
Granted: May 7, 2009
Application Number:
20090119447
Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge…
PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
Granted: May 7, 2009
Application Number:
20090117734
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the…
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
Granted: April 30, 2009
Application Number:
20090108330
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split…
NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE.
Granted: April 30, 2009
Application Number:
20090109721
An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first…
CONTROL OF TEMPERATURE SLOPE FOR BAND GAP REFERENCE VOLTAGE IN A MEMORY DEVICE
Granted: April 30, 2009
Application Number:
20090109742
Systems and/or methods are presented that can facilitate regulating performance of operations in a memory device based on controlling an operating temperature slope associated with the memory device. A regulator component can facilitate controlling the operating temperature slope level and controlling a reference voltage(s) associated with a word-line(s) and/or bit-line(s) to facilitate execution of operations in a memory, while also controlling a respective current level(s) associated…
NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE
Granted: April 30, 2009
Application Number:
20090109758
A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.
DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES
Granted: April 30, 2009
Application Number:
20090109760
Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one…
SIGNAL DESCRAMBLING DETECTOR
Granted: April 30, 2009
Application Number:
20090109769
Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The…
SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK
Granted: April 30, 2009
Application Number:
20090111265
Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions…
