ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
Granted: April 30, 2009
Application Number:
20090113272
Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to…
SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS
Granted: April 23, 2009
Application Number:
20090101963
Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a…
PHOTOVOLTAIC THIN COATING FOR COLLECTOR GENERATOR
Granted: April 23, 2009
Application Number:
20090104432
Photovoltaic coatings and methods of making photovoltaic coatings are provided. The photovoltaic coating contains a semiconductor layer containing semiconductor elements such as silicon particles between bottom metal-semiconductor compounds and upper metal-semiconductor compounds. The upper metal-semiconductor compounds can exist at uppermost boundary portions between semiconductor elements and not substantially over uppermost surfaces of the semiconductor elements. The method can…
HYBRID FLASH MEMORY DEVICE
Granted: April 23, 2009
Application Number:
20090106481
A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory…
SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES
Granted: April 23, 2009
Application Number:
20090106483
Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A…
TAMPER REACTIVE MEMORY DEVICE TO SECURE DATA FROM TAMPER ATTACKS
Granted: April 23, 2009
Application Number:
20090106563
Systems and methods that can facilitate securing data associated with a memory from tampering are presented. A counter tamper component can detect tamper attacks or tamper attempts associated with a memory and/or data stored therein or associated therewith and reacts to such tamper attacks/attempts, as the counter tamper component can provide evidence of, provide a response to, and/or resist tamper attacks/attempts. The counter tamper component can be associated with a memory module that…
OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
Granted: April 23, 2009
Application Number:
20090106577
Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the determination of different clock frequencies that an electronic device(s) can accommodate for transmitting data to and receiving data from the electronic device. The host component can facilitate transmitting data to the electronic device at a higher clock frequency than the clock frequency utilized…
LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE
Granted: April 23, 2009
Application Number:
20090106626
An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on…
RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS
Granted: April 16, 2009
Application Number:
20090097637
Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates data encryption, data decryption, and/or generation of digital signatures, associated with messages. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and/or generation of digital signatures by exponentiating exponents associated with messages. A random number is generated and utilized to randomize…
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
Granted: March 26, 2009
Application Number:
20090081824
The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in…
SECURE MODULAR EXPONENTIATION BY RANDOMIZATION OF EXPONENT SCANNING
Granted: March 12, 2009
Application Number:
20090067617
Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and generation of digital signatures by exponentiating exponents associated with messages. An exponent is divided into more than one subexponent at an exponent bit…
GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT
Granted: March 5, 2009
Application Number:
20090061631
Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage…
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
Granted: March 5, 2009
Application Number:
20090061650
Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a…
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS
Granted: February 26, 2009
Application Number:
20090050471
A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove…
DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS
Granted: February 26, 2009
Application Number:
20090051043
Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Granted: February 26, 2009
Application Number:
20090051051
A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip.
REGULATION OF BOOST-STRAP NODE RAMP RATE USING CAPACITANCE TO COUNTER PARASITIC ELEMENTS IN CHANNEL
Granted: February 19, 2009
Application Number:
20090046511
Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further…
EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION
Granted: February 19, 2009
Application Number:
20090049231
Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, and soft programming operations at address bit combinations available for the respective operations. The characterization component can utilize external address bits that can be fixed when performing the…
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB
Granted: February 12, 2009
Application Number:
20090039405
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the…
READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
Granted: February 12, 2009
Application Number:
20090040839
Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memory cells, non-overlapped. System components can measure distributions rendered non-overlapped to uniquely identify states of such distributions. Identified state distributions can subsequently be disabled to…
