USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
Granted: February 12, 2009
Application Number:
20090042378
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy…
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
Granted: February 5, 2009
Application Number:
20090034334
A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted…
FUEL CELL USING DEUTERIUM
Granted: January 29, 2009
Application Number:
20090029202
Disclosed are fuel cells and methods of using fuel cells involving the use of an anode input gas comprising deuterium.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Granted: January 22, 2009
Application Number:
20090020890
A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar…
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR DEVICE
Granted: January 8, 2009
Application Number:
20090010069
The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the memory cell 18 and a level of the memory cell 18 CORE and using a second data DATA2 obtained by sensing a second reference level REF2 for reading out the data of the memory cell 18 and the level of the memory cell…
SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME
Granted: January 8, 2009
Application Number:
20090010076
A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the…
METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE
Granted: January 8, 2009
Application Number:
20090011600
The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and…
DIE ATTACHMENT, DIE STACKING, AND WIRE EMBEDDING USING FILM
Granted: January 1, 2009
Application Number:
20090001599
Systems, methods, and/or devices that facilitate stacking dies in a multi-die stack using film over wire and attaching a die to a substrate are presented. Film over wire (FOW) techniques can be employed to facilitate stacking dies that are the same or similar in size such that the wires bonded onto the lower die can be embedded in film used to attach the two dies. FOW techniques can also be employed to embed a smaller die and wires attached thereto in film underneath a larger die stacked…
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Granted: January 1, 2009
Application Number:
20090004838
A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR MANUFACTURING DEVICE
Granted: December 25, 2008
Application Number:
20080316790
The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality…
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF
Granted: December 25, 2008
Application Number:
20080320208
A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used…
PROCESS APPLYING DIE ATTACH FILM TO SINGULATED DIE
Granted: December 25, 2008
Application Number:
20080318364
Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method…
COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES
Granted: December 25, 2008
Application Number:
20080316830
Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their…
FAULTY DANGLING METAL ROUTE DETECTION
Granted: December 25, 2008
Application Number:
20080315906
A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The…
STRUCTURE AND PROCESS FOR A RESISTIVE MEMORY CELL WITH SEPARATELY PATTERNED ELECTRODES
Granted: December 18, 2008
Application Number:
20080308781
Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion…
METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES
Granted: November 20, 2008
Application Number:
20080286921
The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal…
Flash memory cell with a flair gate
Granted: November 13, 2008
Application Number:
20080277712
An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first…
MANAGING FLASH MEMORY PROGRAM AND ERASE CYCLES IN THE TIME DOMAIN
Granted: November 13, 2008
Application Number:
20080279005
A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject to an erase cycle. A reclamation management component can reclaim memory region that have invalid data stored therein, and can reclaim regions on a just-in-time basis when practical, and can determine…
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
Granted: November 13, 2008
Application Number:
20080279014
Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
Granted: November 13, 2008
Application Number:
20080280410
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing…
