TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES
Granted: October 30, 2008
Application Number:
20080266926
Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are…
NONVOLATILE MEMORY DEVICE AND METHOD TO CONTROL THE SAME
Granted: October 30, 2008
Application Number:
20080266934
A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being…
ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY
Granted: October 30, 2008
Application Number:
20080266945
Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a…
METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
Granted: October 30, 2008
Application Number:
20080268630
Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first…
TRIPLE POLY-SI REPLACEMENT SCHEME FOR MEMORY DEVICES
Granted: October 30, 2008
Application Number:
20080268650
A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery…
Semiconductor memory device and manufacturing method thereof
Granted: October 30, 2008
Application Number:
20080265309
After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory…
NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE
Granted: October 9, 2008
Application Number:
20080247233
A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device 1 comprises a booster controller circuit 10, a booster circuit 20, a level-shifting circuit 30, a Y-decoder 40, and a main circuit 50. A NAND gate ND1, a NOR gate NR1, and a NOR gate NR2 provided in the booster controller circuit 10 output kick signals KICK0 to KICK2. The booster circuit 20 comprises boosting systems B0, B1, B2…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
Granted: September 25, 2008
Application Number:
20080230898
A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected…
SINGULATED BARE DIE TESTING
Granted: September 25, 2008
Application Number:
20080233663
There is testing of individual dice prior to their inclusion in a multi-chip package. A wafer is sawn into individual dice and the dice are placed onto a die tray. If the tray is not full, then dice can be added that originate from other wafers. Contacts perform diagnostic tests upon the dice to determine if individual dice function as expected. Mapping talkes place to distinguish between dice that passed the diagnostic test and those that did not. Multiple tests can take place in…
HIGH ACCURACY ADAPTIVE PROGRAMMING
Granted: September 18, 2008
Application Number:
20080225596
Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.
STATE CHANGE SENSING
Granted: September 18, 2008
Application Number:
20080229122
Application of too much voltage to a memory cell will cause damage to the cell or even destroy the cell. Tracking current that arises from an application of voltage upon a memory cell allows for minimization of damage upon the memory cell. If there is a change in current, then the voltage application can be accordingly changed.
MEMORY STORAGE VIA AN INTERNAL COMPRESSION ALGORITHM
Granted: September 18, 2008
Application Number:
20080228998
The subject specification discloses flash memory device with the capability of performing both internal compression as well as internal de-compression. Each of these actions takes place through appropriate algorithms. In normal operation, the compression occurs prior to a writing of data in a flash memory device. The compressed data travels to a storage location. The de-compression occurs after the reading of stored data and de-compressed data travels to an external system.
DIVISION-BASED SENSING AND PARTITIONING OF ELECTRONIC MEMORY
Granted: September 18, 2008
Application Number:
20080225607
Providing distinction between overlapping threshold levels of one or more multi-cell memory devices is described herein. By way of example, a system can include a sensing component that can measure a level associated with a first memory cell. The system can also include a comparison component that can compare the measured level associated with the first memory cell level to non-overlapping threshold levels, wherein such measurement can be used to determine a unique bit level associated…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
Granted: September 18, 2008
Application Number:
20080224275
A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Granted: September 11, 2008
Application Number:
20080217673
A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Granted: September 11, 2008
Application Number:
20080217792
A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the…
SEMICONDUCTOR MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD OF THE SAME
Granted: September 4, 2008
Application Number:
20080210170
A semiconductor manufacturing equipment includes a first chamber that has a first connection hole, a second chamber that has a second connection hole connected to the first connection hole of the first chamber, an O-ring that is provided between the first chamber and the second chamber so as to surround the first connection hole and the second connection hole, and a cover portion that covers a space between the first chamber and the second chamber.
Memory Device with Barrier Layer
Granted: August 14, 2008
Application Number:
20080191269
A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate…
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Granted: August 14, 2008
Application Number:
20080191321
The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.
Ic Carrier, Ic Socket and Method for Testing Ic Device
Granted: August 14, 2008
Application Number:
20080191723
An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a package. The IC device has, on a second surface opposite the first surface, (a) a central protrusion (30), (b) a peripheral portion (32) lower than the protrusion by one step, and (c) upper electrodes (18) formed on the peripheral portion of the IC device. The IC carrier is provided with a frame (36), a cover (40), and a holding means…
