SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME
Granted: August 14, 2008
Application Number:
20080192537
A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.
FULLY ASSOCIATIVE BANKING FOR MEMORY
Granted: July 24, 2008
Application Number:
20080177930
A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by…
BYTE MASK COMMAND FOR MEMORIES
Granted: July 24, 2008
Application Number:
20080177931
A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking…
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
Granted: July 10, 2008
Application Number:
20080166853
A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and…
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
Granted: July 3, 2008
Application Number:
20080157160
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first interlayer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect…
BIT LINES FOR SEMICONDUCTOR DEVICES
Granted: July 3, 2008
Application Number:
20080157187
A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
METHOD TO ACHIEVE A LOW COST TRANSISTOR ISOLATION DIELECTRIC PROCESS MODULE WITH IMPROVED PROCESS CONTROL, PROCESS COST, AND YIELD POTENTIAL
Granted: July 3, 2008
Application Number:
20080157289
A method of processing a semiconductor structure is provided. The method includes forming a polish stop layer over one or more features on a substrate; forming a first dielectric layer over the polish stop layer, a valley portion of the first dielectric layer being just above a top of the polish stop layer; and polishing the dielectric layer down to the top of the polish stop layer. By forming a just enough dielectric layer to allow gap-fill on the substrate and polishing the dielectric…
MULTI-LEVEL OPERATION IN DUAL ELEMENT CELLS USING A SUPPLEMENTAL PROGRAMMING LEVEL
Granted: July 3, 2008
Application Number:
20080158954
The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge…
PERSONAL DIGITAL RIGHTS MANAGEMENT AGENT-SERVER
Granted: July 3, 2008
Application Number:
20080162353
Systems and methods that facilitate the management of digital content in a local environment between a limited number of parties. A digital rights management (DRM) agent-server can be created in hardware in which both the agent-server and agent are trusted. A content owner can send digital content along with a rights attachment indicating a scope of the use rights associated with the content. The content can be accessed by the agent and perceived in a presentation component that will…
SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
Granted: July 3, 2008
Application Number:
20080162784
Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an…
USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS
Granted: June 26, 2008
Application Number:
20080151669
Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and…
MEMORY SYSTEM WITH FIN FET TECHNOLOGY
Granted: June 26, 2008
Application Number:
20080150029
A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
MEMORY SYSTEM WITH DEPLETION GATE
Granted: June 26, 2008
Application Number:
20080150005
A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.
MEMORY SYSTEM WITH SELECT GATE ERASE
Granted: June 26, 2008
Application Number:
20080150000
A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.
MEMORY DEVICE ETCH METHODS
Granted: June 26, 2008
Application Number:
20080153298
A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane…
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
Granted: June 26, 2008
Application Number:
20080153224
An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
Granted: June 26, 2008
Application Number:
20080150042
A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
Granted: June 26, 2008
Application Number:
20080150011
A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
MEMORY SYSTEM WITH POLY METAL GATE
Granted: June 26, 2008
Application Number:
20080149990
A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.
ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR FLASH MEMORY
Granted: June 26, 2008
Application Number:
20080149986
A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a…
