FLOATING GATE PROCESS METHODOLOGY
Granted: June 26, 2008
Application Number:
20080153183
A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly layer, removing an interpoly dielectric layer, removing a first poly layer, removing an oxide layer, and removing an unimplanted portion of a substrate. The exposed layer/portion of the…
COPPER PROCESS METHODOLOGY
Granted: June 26, 2008
Application Number:
20080153185
A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction…
NEAR FIELD COMMUNICATION, SECURITY AND NON-VOLATILE MEMORY INTEGRATED SUB-SYSTEM FOR EMBEDDED PORTABLE APPLICATIONS
Granted: June 26, 2008
Application Number:
20080155257
An architecture is presented that facilitates integrating memory, security functionalities and near field communication (NFC) capabilities in a mobile device. A memory module is provided that comprises non-volatile memory that stores security software, sensitive data, and keys and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. A NFC radio frequency transmitter and receiver (RF) is…
NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
Granted: June 26, 2008
Application Number:
20080155258
An architecture is presented that facilitates maintaining a log of near field transactions in a memory module that includes security functionalities and near field communication (NFC) capabilities. The memory module comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. The non-volatile memory is divided into partitions by…
SECURE DATA VERIFICATION VIA BIOMETRIC INPUT
Granted: June 26, 2008
Application Number:
20080155268
An architecture is presented that controls access to secure data via biometric verification. The system comprises a memory module that communicates with biometric data to establish a heightened level of security for controlling access to data stored in the non-volatile memory. The memory module includes a security processor, non-volatile memory, and volatile memory. The security processor provides for concurrent processing of security protocols, provides a secure execution environment…
SOLID-STATE MEMORY-BASED GENERATION AND HANDLING OF SECURITY AUTHENTICATION TOKENS
Granted: June 26, 2008
Application Number:
20080155271
An architecture is presented that facilitates secure token generation and transmission capabilities in a mobile device. The system comprises at least one software application that includes a secure token assigned to a specific user and a memory module that communicates with an external processor. A security processor, non-volatile memory component and volatile memory component are integrated to form the memory module that communicates with the external processor. The memory module…
SYSTEMS AND METHODS FOR DISTINGUISHING BETWEEN ACTUAL DATA AND ERASED/BLANK MEMORY WITH REGARD TO ENCRYPTED DATA
Granted: June 26, 2008
Application Number:
20080155275
Systems and methods that facilitate processing data, such as by encryption/decryption, and storing and retrieving data to/from memory such that actual data can be distinguished from information associated with, or representative of, erased/blank memory locations. A processor can include a comparing component that compares information input to the processor to determine whether such information is associated with actual data, or associated with, or representative of, erased/blank memory…
INTEGRATED CIRCUIT WAFER SYSTEM WITH CONTROL STRATEGY
Granted: June 26, 2008
Application Number:
20080153180
An integrated circuit wafer system includes an integrated circuit wafer, measuring thicknesses of the integrated circuit wafer, calculating a change in temperature ramp rates and thickness offsets for subsequent processing based on the temperature ramp rates for prior processing and the resultant thicknesses, and calculating an average temperature and deposition time for subsequent processing based on calculated changes in temperature ramp rates, coupled with the average temperature,…
STRAPPING CONTACT FOR CHARGE PROTECTION
Granted: June 19, 2008
Application Number:
20080142889
A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
PORTABLE DIGITAL RIGHTS MANAGEMENT (DRM)
Granted: June 19, 2008
Application Number:
20080148414
An architecture is presented that facilitates the transfer of content and rights from a network device to a non-network device. The system comprises a trusted digital rights management (DRM) agent/server that is associated with a network device. The trusted DRM agent/server communicates with a non-network device to transfer content and rights. Specifically, the trusted DRM agent/server of the network device communicates with a second trusted DRM agent/server associated with the…
INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE
Granted: June 19, 2008
Application Number:
20080142874
A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE
Granted: June 19, 2008
Application Number:
20080142873
A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
PREVENTION OF OXIDATION OF CARRIER IONS TO IMPROVE MEMORY RETENTION PROPERTIES OF POLYMER MEMORY CELL
Granted: June 12, 2008
Application Number:
20080135834
Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable…
MEMORY DEVICE PROTECTION LAYER
Granted: June 12, 2008
Application Number:
20080135913
A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.
P-CHANNEL NAND IN ISOLATED N-WELL
Granted: June 12, 2008
Application Number:
20080135918
A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality…
MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK AND METHODS FOR FORMING SAME
Granted: May 29, 2008
Application Number:
20080121981
A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
Granted: May 29, 2008
Application Number:
20080123384
A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
USING SHARED MEMORY WITH AN EXECUTE-IN-PLACE PROCESSOR AND A CO-PROCESSOR
Granted: May 29, 2008
Application Number:
20080126749
The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in place to enable it to execute code directly from the memory, and can arbitrate access to the memory bus and thus the memory, so that the host processor can perform all memory fetches to the memory without…
MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
Granted: May 22, 2008
Application Number:
20080117678
A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).
MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
Granted: May 8, 2008
Application Number:
20080109662
A machine implemented system and method that effectuates secure access to a flash memory associated with a mobile device. The system includes a security component that intercepts transactions between an external processor and the flash memory and implements authentication and access control to the flash memory. The system further includes components that can partition the flash memory and can associate authentication and access control information with the partitioned flash memory.
