Variable read latency on a serial memory bus
Granted: May 13, 2014
Patent Number:
8725920
Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
Simulation method and simulation apparatus
Granted: May 13, 2014
Patent Number:
8725485
A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.
Adaptively programming or erasing flash memory blocks
Granted: May 13, 2014
Patent Number:
8724388
Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.
Hardware based wear leveling mechanism for flash memory using a free list
Granted: May 6, 2014
Patent Number:
8719489
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
Output circuit of high-frequency transmitter
Granted: May 6, 2014
Patent Number:
8718571
A transmitting and receiving device includes: a transmission circuit that transmits a signal by FM-modulating a carrier wave of the signal; an FM demodulation circuit that generates a demodulation signal by FM-demodulating the received signal; and a first filter circuit that changes a pass-band for letting the received signal pass through according to the demodulation signal, wherein the transmitting and receiving device perform a power supply line communication through the power supply…
Node system and supervisory node
Granted: May 6, 2014
Patent Number:
8718038
A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
Semiconductor memory device having non-volatile memory circuits in single chip
Granted: May 6, 2014
Patent Number:
8717833
Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the…
Metal-insulator-metal-insulator-metal (MIMIM) memory device
Granted: May 6, 2014
Patent Number:
8717803
The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in…
Semiconductor device, method of controlling the same, and method of manufacturing the same
Granted: May 6, 2014
Patent Number:
8716082
The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact…
Switchable memory diodes based on ferroelectric/conjugated polymer heterostructures and/or their composites
Granted: April 29, 2014
Patent Number:
8710628
An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and…
Contact configuration for undertaking tests on circuit board
Granted: April 29, 2014
Patent Number:
8708710
An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding…
Selection of a lookup table with data masked with a combination of an additive and multiplicative mask
Granted: April 22, 2014
Patent Number:
8705731
Processing of masked data using multiple lookup tables (LUTs), or sub-tables, is described. For each input value, an appropriate sub-table provides an output value that is the result of a non-linear transformation (e.g., byte substitution) applied to the input value. An additive mask can be applied to the input data. A transformation can be applied to the masked input data to transform the additive mask into a multiplicative-additive mask. Selected bits of the masked input data and the…
Semiconductor device and control method of the same
Granted: April 22, 2014
Patent Number:
8705303
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion…
Capacitive element using MOS transistors
Granted: April 15, 2014
Patent Number:
8698280
In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are…
Memory buffering system that improves read/write performance and provides low latency for mobile systems
Granted: April 15, 2014
Patent Number:
8700830
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
Communication device, communication system, and communication method
Granted: April 15, 2014
Patent Number:
8699549
A communication device includes a transmission circuit that transmits a transmission signal under a certain transmission condition, a reception circuit that receives a reception result of the transmission signal under a certain reception condition and the certain reception condition, and an adjustment circuit that transmits information used to adjust the reception condition based on the reception result and the reception condition from the transmission circuit.
Semiconductor device and control method of the same
Granted: April 15, 2014
Patent Number:
8699283
The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the…
Bitline voltage regulation in non-volatile memory
Granted: April 15, 2014
Patent Number:
8699273
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor…
Switching regulator
Granted: April 15, 2014
Patent Number:
8698473
A switching regulator: first switching element and second switching element; a logic unit which outputs to the load the output voltage converted from the input voltage to the constant voltage, by causing the first switching element and the second switching element to perform a switching operation; an error amplifier which outputs first signal indicating an error between the output voltage and the first reference voltage; first comparator which inputs the first signal and second signal…
Control circuit for power supply including a detection circuit and a regulation circuit for regulating switching timing
Granted: April 15, 2014
Patent Number:
8698465
A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the…
