Authenticated memory and controller slave
Granted: April 8, 2014
Patent Number:
8694776
Systems and methods that can facilitate the utilization of a memory as a slave to a host are presented. The host and memory can provide authentication information to each other and respective rights can be granted based in part on the respective authentication information. The host can determine the available functionality of the memory. The host can activate the desired functionality in the memory and can request memory to perform the desired function(s) with regard to data stored in…
Retargeting of a write operation retry in the event of a write operation failure
Granted: April 8, 2014
Patent Number:
8694714
Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a…
Gate fringing effect based channel formation for semiconductor device
Granted: April 8, 2014
Patent Number:
8692310
Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the…
Memory devices containing a high-K dielectric layer
Granted: April 8, 2014
Patent Number:
8691647
In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain…
Method of manufacturing convex shaped thin-film transistor device
Granted: April 8, 2014
Patent Number:
8691645
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the…
Non-volatile FINFET memory device and manufacturing method thereof
Granted: April 1, 2014
Patent Number:
8686492
Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type…
Self-aligned double patterning for memory and other microelectronic devices
Granted: March 25, 2014
Patent Number:
8680671
A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first…
Parallel bitline nonvolatile memory employing channel-based processing technology
Granted: March 25, 2014
Patent Number:
8681558
Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling…
Control circuit of step-down DC-DC converter, control circuit of step-up DC-DC converter and step-up/step-down DC-DC converter
Granted: March 25, 2014
Patent Number:
8680832
A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an…
Method and system for thin multi chip stack package with film on wire and copper wire
Granted: March 25, 2014
Patent Number:
8680686
A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
Motor control device with a correcting unit determining a corrected rotation angle after a predetermined time from a detection time, control program therefor, and method for the control
Granted: March 18, 2014
Patent Number:
8674632
A motor control device determines a rotation angle and an angular speed of a motor, and has: a correcting unit including N number (N is an positive integer equal to or more than 2) of bit-shift circuits, which divide the angular speed by powers of 2 by bit shift, and a circuit, which subtracts output values of the second to Nth bit-shift circuits from an output value of the first bit-shift circuit to determine a correction amount for the rotation angle and correct the rotation angle by…
Memory manufacturing process with bitline isolation
Granted: March 18, 2014
Patent Number:
8673716
A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A…
Cryptographic system with modular randomization of exponentiation
Granted: March 11, 2014
Patent Number:
8670557
Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and generation of digital signatures by exponentiating exponents associated with messages. An exponent is divided into more than one subexponent at an exponent bit…
Semiconductor device and method for manufacturing thereof
Granted: March 11, 2014
Patent Number:
8669606
An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the…
Memory device interconnects and method of manufacturing
Granted: March 11, 2014
Patent Number:
8669597
An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the…
Fabricating method of mirror bit memory device having split ONO film with top oxide film formed by oxidation process
Granted: March 11, 2014
Patent Number:
8669161
A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
Body-bias voltage controller and method of controlling body-bias voltage
Granted: February 25, 2014
Patent Number:
8659346
A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.
Etch stop layer for memory cell reliability improvement
Granted: February 25, 2014
Patent Number:
8658496
A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
HTO offset for long Leffective, better device performance
Granted: February 18, 2014
Patent Number:
8653581
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level…
Frequency distributed flash memory allocation based on free page tables
Granted: February 18, 2014
Patent Number:
8656083
Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are…
