Dynamically reconfigurable shared scan-in test architecture
Granted: December 1, 2005
Application Number:
20050268190
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
Hierarchical signal integrity analysis using interface logic models
Granted: October 13, 2005
Application Number:
20050229128
Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information for the blocks. To further increase the speed and accuracy of SI analysis, enhanced interface logic models (SI-ILMs) can be used. An…
Model-based two-dimensional interpretation filtering
Granted: October 13, 2005
Application Number:
20050229148
Complex layout features, especially two-dimensional (2D) features such as jogs and corners, are more susceptible to photo-resist pinching and bridging, even with the use of optical proximity correction. These problems may arise due to unrealistic targets, e.g. square corners, thereby resulting in excessively aggressive correction in the vicinity of these 2D features. To provide a more realistic target, an aerial image can be sampled and its gradient computed at evaluation points on the…
Simulation based PSM clear defect repair method and system
Granted: September 8, 2005
Application Number:
20050196688
Mask shops typically use carbon to repair any clear defects identified on a mask, irrespective of the type of mask. However, carbon can have different characteristics than the original patterning material on the mask. Therefore, a mask that is repaired using carbon may not optically perform as if it were defect-free. An automated method of repairing a clear defect on an attenuated phase shifting mask (PSM) provides an optimized plug size/shape. In this method, a repair solution to the…
System and method of providing mask defect printability analysis
Granted: September 1, 2005
Application Number:
20050190957
A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information…
System and method for providing distributed static timing analysis with merged results
Granted: August 4, 2005
Application Number:
20050172250
Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel…
Design data format and hierarchy management for processing
Granted: July 28, 2005
Application Number:
20050166173
Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an…
Method for printability enhancement of complementary masks
Granted: June 16, 2005
Application Number:
20050130047
When substantially all features in a layout for a layer of material in an integrated circuit (IC) are defined using a phase shifting mask, the related complementary mask that is normally used to define the remaining features and edges can be improved if intensities in an aerial image from openings on the complementary mask that are below threshold are increased to ensure that each opening meets or exceeds threshold. Such increase of intensities improves effectiveness of critical openings…
Full phase shifting mask in damascene process
Granted: June 9, 2005
Application Number:
20050123841
A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to…
System and method for optimizing exceptions
Granted: October 21, 2004
Application Number:
20040210861
A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and…
METHOD AND SYSTEM FOR GENERATING AN ATPG MODEL OF A MEMORY FROM BEHAVIORAL DESCRIPTIONS
Granted: August 26, 2004
Application Number:
20040167764
42Method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). Behavioral models of memories of simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e.g., Verilog). Simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. Structural models are stored for subsequent access during pattern generation. In another…
OPTIMIZATION OF TIMING MODELS USING BUS COMPRESSION
Granted: June 10, 2004
Application Number:
20040111247
A method of compressing bus-related model data for transistor-level timing arcs in a circuit timing model. Compressed model syntax and timing information are provided for the following node-to-node transistor level representations: many-to-many bitwise, many-to-many, one-to-many, and many-to-one. In the many-to-many bitwise embodiment, each of the consecutive start nodes is coupled to a different end node. In the many-to-many embodiment, the plurality of consecutive transistor-level…
SYSTEM AND METHOD FOR HARDWARE AND SOFTWARE CO-VERIFICATION
Granted: May 6, 2004
Application Number:
20040088150
The present invention provides a hardware software co-verification tool for use by software and hardware designers of a computing system that uses an operating system having a strongly specified hardware interface specification. The present invention receives and tests the functionality of the software code intended for interaction with a hardware component within the computer system. An actual physical implementation of the hardware component is not used but is substituted with a…
Detailed placer for optimizing high density cell placement in a linear runtime
Granted: April 22, 2004
Application Number:
20040078770
A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two or more rows. The search space is pruned beforehand. A greedy cleanup phase using an incremental row placer is used. Thereby, the detailed placement process handles…
