Modeling circuit cells for waveform propagation
Granted: January 11, 2007
Application Number:
20070010981
A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of…
Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects
Granted: January 4, 2007
Application Number:
20070006118
Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias.…
Engineering change order process optimization
Granted: December 7, 2006
Application Number:
20060277512
A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation…
Leakage power reduction in CMOS circuits
Granted: November 30, 2006
Application Number:
20060267108
A field effect transistor includes a source region and a drain region in contact with a channel region. The source and drain regions are formed in insulating pockets that cause the source and drain regions to be electrically isolated from the substrate, thereby minimizing junction capacitance and device crosstalk. The structures that define the insulating pockets can be insulating layers formed in one or more wells in the substrate, or can be a blanket insulating formed over the…
Relative positioning of circuit elements in circuit design
Granted: November 30, 2006
Application Number:
20060271894
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology.
Centerline-based pinch/bridge detection
Granted: November 30, 2006
Application Number:
20060271906
A method for performing layout verification involves identifying feature centerlines in a mask layout, and then performing lithography simulation along the centerlines to generate a set of intensity distributions. At each local maxima or minima in the intensity distributions, further lithography simulation can be performed to determine an exposure pattern width at those local maxima/minima (check positions). The exposure pattern widths can then be evaluated to determine whether an actual…
Phase abstraction for formal verification
Granted: November 9, 2006
Application Number:
20060253815
A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce…
System And Method For Providing Defect Printability Analysis Of Photolithographic Masks With Job-Based Automation
Granted: October 26, 2006
Application Number:
20060242619
Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the…
Determining equivalent waveforms for distorted waveforms
Granted: September 7, 2006
Application Number:
20060200784
An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period…
Latch modeling technique for formal verification
Granted: August 24, 2006
Application Number:
20060190870
A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because…
Stacked memory cell utilizing negative differential resistance devices
Granted: June 15, 2006
Application Number:
20060125017
A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell.
Segmentation and interpolation of current waveforms
Granted: May 4, 2006
Application Number:
20060095243
A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for…
Nonlinear driver model for multi-driver systems
Granted: May 4, 2006
Application Number:
20060095869
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate…
Nonlinear receiver model for gate-level delay caculation
Granted: May 4, 2006
Application Number:
20060095871
A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first…
Fast evaluation of average critical area for IC layouts
Granted: May 4, 2006
Application Number:
20060095877
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution…
Wide geometry recognition by using circle-tangent variable spacing model
Granted: April 27, 2006
Application Number:
20060090148
Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A trim region within each projection region is defined using the associated detection circle, such that a portion of the trim region boundary exhibits tangency to the detection…
Detailed placer for optimizing high density cell placement in a linear runtime
Granted: April 27, 2006
Application Number:
20060090151
A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two or more rows. The search space is pruned beforehand. A greedy cleanup phase using an incremental row placer is used. Thereby, the detailed placement process handles…
Preconditioning for EDA cell library
Granted: March 16, 2006
Application Number:
20060057594
A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the…
System and method for reducing size of simulation value change files
Granted: January 5, 2006
Application Number:
20060004557
During simulation of an IC design, traces of certain signals can be generated, thereby allowing defects in the design to be detected. The traces of these signals, i.e. the target set, are typically saved in a value change file. Unfortunately, this value change file can get very large, thereby causing capacity and performance problems. A technique is described in which a subset of signals that can regenerate the target set of signals is determined. Determining the subset of signals can…
Reconstructing transaction order using clump tags
Granted: December 15, 2005
Application Number:
20050278511
A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.
