Logic Timing and Reliability Repair for Nanowire Circuits
Granted: October 31, 2019
Application Number:
20190333600
A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be…
Methodology To Create Constraints And Leverage Formal Coverage Analyzer To Achieve Faster Code Coverage Closure For An Electronic Structure
Granted: September 12, 2019
Application Number:
20190278884
An efficient unreachability analysis tool utilizes toggle coverage report data to automatically generate constraints associated with viable constant signals (e.g., constant inputs, one-time programmable and constant registers) utilized in a circuit design before performing a full unreachability analysis process, thereby improving the functioning of the computer/processor executing the unreachability analysis process by identifying low-activity registers and constraining them before the…
MEMORY ARRAY ARCHITECTURES FOR MEMORY QUEUES
Granted: September 5, 2019
Application Number:
20190272120
Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In…
MACHINE-LEARNING CIRCUIT OPTIMIZATION USING QUANTIZED PREDICTION FUNCTIONS
Granted: July 25, 2019
Application Number:
20190228126
An EDA tool trains a machine-learning optimization tool using quantized optimization solution (training) data generated by conventional optimization tools. Each training data entry includes an input vector and an associated output vector that have quantized component values respectively determined by associated operating characteristics of initial (non-optimal) and corresponding replacement (optimized) circuit portions, where each initial circuit portion is identified and replaced by the…
METHOD AND APPARATUS OF USING PARITY TO DETECT RANDOM FAULTS IN MEMORY MAPPED CONFIGURATION REGISTERS
Granted: July 25, 2019
Application Number:
20190227867
A fault detection circuit generates a current parity bit for configuration data currently stored in a configuration register during each clock cycle, and compares the current parity bit with a previous parity bit generated during a previous clock cycle. An error signal is asserted when a mismatch is detected, indicating that the configuration register data erroneously changed due to a random hardware fault. Detection output circuitry is used to disable the error signal output driver…
PERFORMANCE AWARE WORD LINE UNDER-DRIVE READ ASSIST SCHEME FOR HIGH DENSITY SRAM TO ENABLE LOW VOLTAGE FUNCTIONALITY
Granted: July 18, 2019
Application Number:
20190221256
PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and…
Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions
Granted: May 16, 2019
Application Number:
20190148371
Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about…
Atomic Scale Grid for Modeling Semiconductor Structures and Fabrication Processes
Granted: May 16, 2019
Application Number:
20190147123
Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An…
Mitigating Write Disturbance in Dual Port 8T SRAM
Granted: May 2, 2019
Application Number:
20190130965
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.
INTEGRATED METAL LAYER AWARE OPTIMIZATION OF INTEGRATED CIRCUIT DESIGNS
Granted: February 28, 2019
Application Number:
20190065656
Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4)…
Finfet with Heterojunction and Improved Channel Control
Granted: February 7, 2019
Application Number:
20190043987
Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first…
PARTITIONING IN POST-LAYOUT CIRCUIT SIMULATION
Granted: January 31, 2019
Application Number:
20190034574
The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the…
Atomic Structure Optimization
Granted: January 3, 2019
Application Number:
20190005202
Computer system provided with a control module for controlling ab initio atomic structure modules for simulating the behavior of structures and materials at multiple scales with different modules, for purposes of evaluating such structures and materials for use in integrated circuit devices. The computer system can simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.
PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT STRESS EFFECTS
Granted: November 1, 2018
Application Number:
20180314783
Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place- and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a…
TINED GATE TO CONTROL THRESHOLD VOLTAGE IN A DEVICE FORMED OF MATERIALS HAVING PIEZOELECTRIC PROPERTIES
Granted: October 18, 2018
Application Number:
20180300443
Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least…
Computationally Efficient Nano-Scale Conductor Resistance Model
Granted: September 6, 2018
Application Number:
20180253524
Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each…
DESIGN-FOR-TESTABILITY (DFT) INSERTION AT REGISTER-TRANSFER-LEVEL (RTL)
Granted: August 30, 2018
Application Number:
20180246996
Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein…
Automated Resistance and Capacitance Extraction and Netlist Generation of Logic Cells
Granted: August 23, 2018
Application Number:
20180239857
Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A…
EXACT DELAY SYNTHESIS
Granted: August 23, 2018
Application Number:
20180239846
Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be…
Method and Apparatus with Channel Stop Doped Devices
Granted: August 9, 2018
Application Number:
20180226301
Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
