THREE-DIMENSIONAL NoC RELIABILITY EVALUATION
Granted: July 19, 2018
Application Number:
20180203963
Methods, storage mediums, and apparatuses for evaluating the reliability of Three-Dimensional (3D) Network-on-Chip (NoC) designs are described. The described embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments automate the whole process of static and dynamic fault injection base on the user preference and reports the specific reliability metrics for 3D NoC…
Exponentially Fitted Approximation for Anisotropic Semiconductor Equations
Granted: July 19, 2018
Application Number:
20180203962
Roughly described, a method for determining characteristics of a body by simulation, useful in analyzing semiconductor devices, includes imposing a Delaunay mesh on a simulated body to be modeled, determining a system of node equations describing generation and flux of a set of at least a first physical quantity at each node in the mesh, and numerically solving the system of node equations to identify the physical quantities in the set at each node in the mesh, where the flux of the…
Substrates and Transistors with 2D Material Channels on 3D Geometries
Granted: June 28, 2018
Application Number:
20180182898
Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit…
EXACT DELAY SYNTHESIS
Granted: June 21, 2018
Application Number:
20180173818
Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based…
NANO-WIRE RESISTANCE MODEL
Granted: June 7, 2018
Application Number:
20180157783
An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as…
Efficient Lattice Kinetic Monte Carlo Simulations for Epitaxial Growth
Granted: June 7, 2018
Application Number:
20180157774
A method for simulating an epitaxial process in a body having a crystal lattice structure. Roughly described, an enlarged version of the crystal lattice structure is formed, having a lattice constant increased by a lattice enlargement factor N>1. The subject fabrication process is simulated by a Lattice Kinetic Monte Carlo algorithm in which various factors have been scaled in accordance with N. The simulation speed increases by a factor around N3, without significantly degrading the…
Increasing Compression by Reducing Padding Patterns
Granted: June 7, 2018
Application Number:
20180156869
A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current…
GRAPHICAL USER INTERFACE TO FACILITATE ROUTING OF A PHYSICAL CONNECTION IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
Granted: May 31, 2018
Application Number:
20180150587
Systems and techniques are described for transparently editing physical data in hierarchical IC designs. Some embodiments allow a user to access objects at any level of the physical hierarchy and to specify a particular editing operation (move, rotate, delete, cut, split, etc.) relative to the top-level block. The embodiments can automatically transform and apply the editing operations in the context of the block where the edited object resides. Systems and techniques for automatic…
Modeling Deformation Due To Surface Oxidation In Integrated Circuits
Granted: May 24, 2018
Application Number:
20180144073
Oxidation of high aspect ratio IC structures, such as pillars and fins, can deform them. Disclosed is technology for simulating the deformation efficiently so that process conditions or pattern design can be altered to improve manufacturability. A database describing a 3D model of the structures prior to the oxidation process is provided. Oxidation is simulated in 1D on different surfaces to estimate a depth of starting material that will be converted during oxidation. Starting material…
Simulation Scaling With DFT and Non-DFT
Granted: May 24, 2018
Application Number:
20180144076
Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
CONTEXT-DEPENDENT USEFUL SKEW ESTIMATION FOR OPTIMIZATION, PLACEMENT, AND CLOCK TREE SYNTHESIS
Granted: May 17, 2018
Application Number:
20180137217
A method for optimizing a circuit design includes computing clock latency estimates for a set of sequential circuit elements, modifying the clock latency estimates based on relative optimizability of (1) a set of input data paths that are electrically coupled to one or more inputs of the sequential circuit element and (2) a set of output data paths that are electrically coupled to one or more outputs of the sequential circuit element, and optimizing the circuit design based on the…
Systems and Methods for Providing Approximate Electronic-Structure Models from Calculated Band Structure Data
Granted: May 10, 2018
Application Number:
20180129765
Computer-aided methods for simulating confined nanodevices are disclosed. In example implementations, atomic-scale model of the nanodevices are generated so that dimensions and materials are specified. Then, band structures which comprise wave functions and Eigen energies are calculated using First Principles Methods (FPM). Effective mass modeled which comprise wave functions and Eigen energies are generated. After that, spatial wave functions of the calculated FPM band structures are…
MEMORY CELLS INCLUDING VERTICAL NANOWIRE TRANSISTORS
Granted: May 3, 2018
Application Number:
20180122793
A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors,…
PLACEMENT-BASED CONGESTION-AWARE LOGIC RESTRUCTURING
Granted: May 3, 2018
Application Number:
20180121591
Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a…
Atomic Scale Grid for Modeling Semiconductor Structures and Fabrication Processes
Granted: April 26, 2018
Application Number:
20180113968
Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An…
MULTI-BIT-MAPPING AWARE CLOCK GATING
Granted: April 19, 2018
Application Number:
20180107779
Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.
OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ONE WIDE-GATE OR WIDE-BUS
Granted: April 19, 2018
Application Number:
20180107777
Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent…
Virtual Terminals for Linear-Parameter Extraction
Granted: March 29, 2018
Application Number:
20180089353
A method to evaluate a resistor structure is described. In one embodiment, the method includes receiving an input file specifying a resistor structure, modifying at least one aspect of the resistor structure, and polishing data representing the modified resistor structure. The method further comprises, in one embodiment, initializing at least one walk, and performing the walk, and providing an output about the resistor structure based on the performed at least one walk.
Partitioning Using a Correlation Meta-Heuristic
Granted: March 8, 2018
Application Number:
20180068044
A method for partitioning for a hypergraph including a plurality of nodes into a plurality of bins includes assigning each node of the hypergraph to one of the plurality of bins to generate a candidate solution, and for each pair of nodes in the candidate solution, calculating a weighted covariance based on the bin assignment of each node of the pairs of nodes in the candidate solution. The assigning and the calculating are repeated to generate an accumulated weighted covariance for the…
Optimizing The Ordering Of The Inputs To Large Commutative-Associative Trees Of Logic Gates
Granted: January 4, 2018
Application Number:
20180004862
A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.
