Synopsys Patent Grants

Evaluation of thermal instability stress testing

Granted: November 14, 2017
Patent Number: 9817059
A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Guarded memory access in a multi-thread safe system level modeling simulation

Granted: November 14, 2017
Patent Number: 9817771
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes…

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

Granted: November 14, 2017
Patent Number: 9817928
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

Placing and routing debugging logic

Granted: November 14, 2017
Patent Number: 9817939
Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more…

Timing closure methodology including placement with initial delay values

Granted: November 7, 2017
Patent Number: 9811624
An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based…

Dynamic color depth for HDCP over HDMI

Granted: October 17, 2017
Patent Number: 9794623
A method for determining the color depths of the video data for a selected frame in High-bandwidth Digital Content Protection (HDCP) video data transmitted over a High Definition Multimedia Interface (HDMI), in which (a) the beginning of the selected frame is marked with a vertical synchronization (VSYNC) signal and (b) a mark in a window of opportunity (WOO) for the selected frame indicates whether or not that frame is encrypted. The method detects, for the selected frame, the length of…

Accurate glitch detection

Granted: October 17, 2017
Patent Number: 9792394
Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when…

Method and apparatus for automatic relative placement generation for clock trees

Granted: October 17, 2017
Patent Number: 9792396
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

Reduction of spatial predictors in video compression

Granted: October 10, 2017
Patent Number: 9787985
A system and a method are disclosed for encoding and decoding a video frame using spatial prediction. The video frame is separated into a plurality of image blocks, and a plurality of spatial predictors is created for an image block using methods well-known in the art. The set of predictors is reduced to a set containing fewer spatial predictors before continuing the coding process for the block. The reduction of spatial predictors involves comparing a plurality of spatial predictors and…

Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same

Granted: October 10, 2017
Patent Number: 9786734
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.

Resource management in a multicore architecture

Granted: October 3, 2017
Patent Number: 9779042
A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the…

Rate distortion optimization in image and video encoding

Granted: October 3, 2017
Patent Number: 9781449
An offline quantization module is used to optimize a rate-distortion task. The offline quantization module calculates a quantization kernel for a range of computable block parameters and a range of rate-distortion slope values representing the rate and complexity of a coded video. A quantization kernel is utilized by an encoder application for content-adaptive quantization of transformed coefficients. The quantization kernel includes a block data model, a quality metric model, and an…

X-propagation in emulation using efficient memory

Granted: September 26, 2017
Patent Number: 9773078
Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a…

Regulated voltage supply with low power consumption and small chip area

Granted: September 19, 2017
Patent Number: 9767861
A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor…

Analysis of program code

Granted: September 12, 2017
Patent Number: 9760469
This disclosure relates to the analysis of a program based on source code where the source code comprises a call to a function associated with a function implementation. A processor determines, based on a summary that over-approximates the function, an assignment of an input variable and an output variable of the function call to reach a predefined state. The processor then determines, based on the implementation of the function whether the assignment of the input variable results in the…

Automatic generation of properties to assist hardware emulation

Granted: September 12, 2017
Patent Number: 9760663
Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable…

Determining slack estimates for multiple instances of a cell in a hierarchical circuit design

Granted: September 5, 2017
Patent Number: 9754069
Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of…

Path-based floorplan analysis

Granted: September 5, 2017
Patent Number: 9754070
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.

Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs

Granted: August 29, 2017
Patent Number: 9747403
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG…

Buffer chain management for alleviating routing congestion

Granted: August 29, 2017
Patent Number: 9747405
Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage,…