Modelling timing behavior using augmented sensitivity data for physical parameters
Granted: April 23, 2024
Patent Number:
11966678
A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known…
Emulation performance analysis using abstract timing graph representation
Granted: April 23, 2024
Patent Number:
11966677
A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of…
Phase mixer non-linearity compensation within clock and data recovery circuitry
Granted: April 16, 2024
Patent Number:
11962676
A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines…
Partitioning in post-layout circuit simulation
Granted: April 16, 2024
Patent Number:
11960811
New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the…
Classification of programming language code into basic constructs of source code and non-source code
Granted: April 9, 2024
Patent Number:
11954485
A method for processing a source code file comprises scanning the source code file to identify text lines, and analyzing, via one or more processors, the text lines with a classifier to identify one or more of the text lines that correspond to code construct type information. The code construct type information includes license information. The classifier is trained with sample source code files. The method further comprises generating a subset of the text lines that excludes the one or…
Two-step duty-cycle correction for high-speed clocks in communications systems
Granted: April 2, 2024
Patent Number:
11949421
A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to…
Intelligent software development, security, and operations workflow
Granted: April 2, 2024
Patent Number:
11947946
Disclosed herein are system, computer-implemented method, and computer program product (computer-readable storage medium) embodiments for implementing an intelligent DevSecOps workflow. An embodiment includes receiving, by at least one processor, a risk profile associated with a software deployment, and an update related to the software deployment; and evaluating, by the at least one processor, at least one parameter associated with the update, to produce an evaluation result.…
Low-power static signoff verification from within an implementation tool
Granted: April 2, 2024
Patent Number:
11947885
In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination…
Universal serial bus scheduling using real time data
Granted: April 2, 2024
Patent Number:
11947480
A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes…
Technology validation and ownership
Granted: March 26, 2024
Patent Number:
11943369
A method comprising receiving a plurality of signatures representing one or more proprietary files from a vendor generated without disclosure of the proprietary files, each signature corresponding to a segment of a proprietary file. The method further comprising and validating each of the plurality of the signatures, to ensure that the signatures are the proprietary code of the vendor. The method further comprises adding the plurality of the signatures to a global database, the global…
Energy-efficient SFQ logic biasing technique
Granted: March 26, 2024
Patent Number:
11942936
Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being…
Accelerating static program analysis with artifact reuse
Granted: March 26, 2024
Patent Number:
11941379
A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked…
Automated equal-resistance routing in compact pattern
Granted: March 26, 2024
Patent Number:
11941339
Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is…
Power harvesting for integrated circuits
Granted: March 19, 2024
Patent Number:
11937507
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…
Atomic correction of single bit errors within a memory
Granted: March 12, 2024
Patent Number:
11928024
A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.
Memory efficient scalable distributed static timing analysis using structure based self-aligned parallel partitioning
Granted: March 5, 2024
Patent Number:
11922106
A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.
Using scan chains to read out data from integrated sensors during scan tests
Granted: March 5, 2024
Patent Number:
11921160
Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the…
Clock re-convergence pessimism removal through pin sharing during clock tree planning
Granted: February 27, 2024
Patent Number:
11914939
A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.
Predicting defect rate based on lithographic model parameters
Granted: February 27, 2024
Patent Number:
11914306
A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
Reset domain crossing detection and simulation
Granted: February 20, 2024
Patent Number:
11907631
Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation…
