Continuous time linear equalizer with programmable inductive high frequency boost
Granted: November 26, 2024
Patent Number:
12155509
A communication system includes a receiver device having a continuous time linear equalizer circuitry. The continuous time linear equalizer circuitry includes first gain circuitry, second gain circuitry, second gain circuitry a first capacitor, a first resistive element, a first inductor, and a second resistive element. The first gain circuitry and the second gain circuitry receive an input signal. The first capacitor is connected between an output of the first gain circuitry and an…
Message passing multi processor network for simulation vector processing
Granted: November 26, 2024
Patent Number:
12153864
This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously…
Multi-processor simulation on a multi-core machine
Granted: November 26, 2024
Patent Number:
12153863
The invention relates to methods of simulation of a plurality of processors running on a plurality of cores, to multi-core microprocessor systems in which such methods may be carried out, and to computer program products configured to perform a simulation of a plurality of processors, running on a plurality of cores. According to a first aspect of the invention, there is provided a method of running a plurality of simulated processors on a plurality of cores, in which simulation of the…
At-speed synchronous write-through operation for testing two-port memory
Granted: November 19, 2024
Patent Number:
12148490
A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is…
Co-optimizing power supply voltage in an integrated circuit design
Granted: November 19, 2024
Patent Number:
12147749
A relationship between at least a first metric of an integrated circuit (IC) design and a power supply voltage of the IC design may be determined based on a set of IC designs that have different power supply voltages. Next, the power supply voltage and at least the first metric of the IC design may be modified by interpolating values of the first metric based on the relationship between the first metric and the power supply voltage of the IC design.
System for making circuit design changes
Granted: November 19, 2024
Patent Number:
12147748
A system and method for changing a circuit design are described. The method includes generating a propagation graph for the circuit design and estimating slack values for some of the paths in the propagation graph. The method also includes making a virtual change to the circuit design and determining whether to accept or reject the change based on how the change affects the estimated slack values.
Buffer circuitry for store to load forwarding
Granted: November 19, 2024
Patent Number:
12147707
A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is…
Integrating machine learning delay estimation in FPGA-based emulation systems
Granted: November 12, 2024
Patent Number:
12140628
A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays,…
Angle of arrival (AoA) determination for Bluetooth® Low Energy (BLE)
Granted: November 12, 2024
Patent Number:
12143195
A communication receiver can determine an angle of arrival (AoA) of a communication signal. The communication receiver includes multiple receiving antennas and processing circuitry. The processing circuitry determines multiple phase shifts over multiple instances in time from first samples of a communication signal as observed by a reference receiving antenna selected from among the multiple receiving antennas, samples the communication signal as observed by the selected receiving…
Device under test synchronization with automated test equipment check cycle
Granted: November 12, 2024
Patent Number:
12140632
Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the…
Synchronization of a transfer of data signals between circuits when a clock in a destination circuit is off
Granted: October 29, 2024
Patent Number:
12130658
A method and system are provided for synchronizing signals, using a synchronizer circuit, between a source circuit and a destination circuit that utilizes detection of when the destination circuit clock is turned off. In the method performed by the synchronizer circuit, a stop signal is received from the destination circuit that is generated upon determination that the destination clock in the destination circuit is turned off. A data signal from the source circuit is, upon receipt of…
Key protection using a noising and de-noising scheme
Granted: October 22, 2024
Patent Number:
12126714
A cryptography system comprises a noising engine and a de-noising engine. The noising engine is configured to receive a key pattern, determine a final membership value based on one or more input parameters and a first knowledge base, and generate a noised key pattern based on the key pattern and the final membership value. The de-noising engine is configured to receive the noised key pattern and the final membership value, and generate a de-noised key pattern based on the noised key…
Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis
Granted: October 22, 2024
Patent Number:
12124782
A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.
Power estimation using input vectors and deep recurrent neural networks
Granted: October 22, 2024
Patent Number:
12124780
A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a…
Management circuitry for a least recently used memory management process
Granted: October 22, 2024
Patent Number:
12124379
A processing system employs a method to order the elements within a memory. Ordering the elements includes receiving an accessed memory element. The accessed memory element is requested by a processor from a memory. Further, the accessed memory element is compared to stored elements within the memory to generate control signals. Gate control signals from the control signals are generated. The order of the stored elements within the memory is updated based on the gate control signals.
Predicting aliasing bits in a virtually indexed physically tagged cache
Granted: October 22, 2024
Patent Number:
12124375
A second virtual address may be received, where the second virtual address is different from a first virtual address. A second hash value may be computed based on the second virtual address. A first comparison result may be determined by comparing the second hash value with a first hash value, where the first hash value is computed based on the first virtual address. The first comparison result may be used to select a selected structure from either a first structure or a second…
Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
Granted: October 15, 2024
Patent Number:
12117488
A system and method are provided for testing logic using a logic built in self-test (LBIST) system, and in particular where the LBIST system tolerates unknown inputs (Xs) to the logic cells forming an XLBIST system. The system allows for providing multiple test system clocks from the LBIST system to the logic during a system clock capture cycle of a system clock during testing of the logic, wherein the system clock is separate from the multiple test system clocks of the LBIST system.…
Clock synthesizer with dual control
Granted: October 15, 2024
Patent Number:
12119828
The present disclosure describes circuits (e.g., clock synthesizers) and methods for producing alternating signals. A clock synthesizer includes an oscillator, a voltage control circuit, and a frequency control circuit. The oscillator produces an output signal with a frequency. The voltage control circuit produces a control voltage for the oscillator based on the frequency of the output signal. The frequency control circuit produces a control signal for the oscillator based on (i) an…
Glitch filter with reset circuit
Granted: October 15, 2024
Patent Number:
12119827
An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the…
Automatic channel identification of high-bandwidth memory channels for auto-routing
Granted: October 15, 2024
Patent Number:
12118283
Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method…
