Neural network based mask synthesis for integrated circuits
Granted: May 6, 2025
Patent Number:
12293279
A system uses machine learning models, such as neural networks for generating mask design from a circuit design. The machine learning models have inputs and outputs which are localized to a small region of the circuit design. The machine learning model takes as input features describing the circuit design in the neighborhood of a location and generates an offset distance as output. The system uses the offset distance to generate features of the mask design, for example, main features or…
Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory
Granted: May 6, 2025
Patent Number:
12293139
Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced…
Memory coherence protocol for communicating data associated with a shared state between processor cores
Granted: May 6, 2025
Patent Number:
12292832
A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory…
Integrated circuit design and layout with multiple interpreters
Granted: April 29, 2025
Patent Number:
12288020
A method for generating a circuit layout includes generating a plurality of symbols. Each of the plurality of symbols identifies one of multiple versions of code describing a circuit layout. The method also includes loading the plurality of symbols into a design platform used to compile the code describing the circuit layout. The design platform has evaluators for the multiple versions of the code. The method further includes generating the circuit layout described by the code using the…
Scan chain formation for improving chain resolution
Granted: April 22, 2025
Patent Number:
12282063
The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed…
Synthesis placement bounds based on physical timing analysis
Granted: April 15, 2025
Patent Number:
12277374
Embodiments provide for improved placement bounds. An example method includes identifying, based on a first synthesizing of an integrated circuit layout representation, a plurality of integrated circuit endpoints. The example method further includes identifying, based on a plurality of feature vectors each representing an endpoint of the plurality of integrated circuit endpoints, a plurality of integrated circuit clusters. Each integrated circuit cluster comprises a unique subset of…
Multi-cycle test generation and source-based simulation
Granted: April 15, 2025
Patent Number:
12277372
A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second…
Fail-safe software access licensing control on a per project basis without a priori knowledge of project details
Granted: April 15, 2025
Patent Number:
12277200
A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.
Address mapping for a memory system
Granted: April 15, 2025
Patent Number:
12277055
Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.
Reducing spurious write operations in a memory device
Granted: April 8, 2025
Patent Number:
12272424
A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter…
Finding equivalent classes of hard defects in stacked MOSFET arrays
Granted: April 8, 2025
Patent Number:
12271668
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the…
Signal integrity monitoring system
Granted: April 8, 2025
Patent Number:
12270857
Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.
Built-in self-test circuit for row hammering in memory
Granted: April 1, 2025
Patent Number:
12266413
A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values…
Clock aware simulation vector processor
Granted: April 1, 2025
Patent Number:
12265779
A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of…
Inverse lithography and machine learning for mask synthesis
Granted: April 1, 2025
Patent Number:
12265325
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. These techniques include providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The techniques further include performing, using the ML Model, a plurality of dilated convolutions relating to the design pattern, and inferring, using the ML model, one or more masks for use in manufacturing the semiconductor device, based…
Memory profiler for emulation
Granted: April 1, 2025
Patent Number:
12265122
A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence…
Managing high performance simulation representation of an emulation system
Granted: March 25, 2025
Patent Number:
12259806
A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the…
Dynamic clock scaling using compression and serialization
Granted: March 25, 2025
Patent Number:
12259746
A method of transferring data from a first circuit block to a second circuit block, includes, in part, sampling the data using a first clock signal during a first cycle, compressing the sampled data at the first circuit block and using a compression ratio. In response to a determination that the compression ratio is equal to or less than a threshold value, selecting the compressed data for transmission to the second circuit block, and selecting a second clock signal for sampling the data…
Glitch identification and power analysis using simulation vectors
Granted: March 18, 2025
Patent Number:
12254255
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.
Diagnosis of inconsistent constraints in a power intent for an integrated circuit design
Granted: March 18, 2025
Patent Number:
12254256
A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where…
