Memory efficient scalable distributed static timing analysis using structure based self-aligned parallel partitioning
Granted: March 5, 2024
Patent Number:
11922106
A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.
Using scan chains to read out data from integrated sensors during scan tests
Granted: March 5, 2024
Patent Number:
11921160
Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the…
Clock re-convergence pessimism removal through pin sharing during clock tree planning
Granted: February 27, 2024
Patent Number:
11914939
A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.
Predicting defect rate based on lithographic model parameters
Granted: February 27, 2024
Patent Number:
11914306
A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
Reset domain crossing detection and simulation
Granted: February 20, 2024
Patent Number:
11907631
Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation…
Power validation based on power assertion specification
Granted: February 20, 2024
Patent Number:
11907630
A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power…
Testing of hardware queue systems using on device test generation
Granted: February 20, 2024
Patent Number:
11907088
An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.
Stochastic-aware lithographic models for mask synthesis
Granted: February 13, 2024
Patent Number:
11900042
In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
Stochastic-aware lithographic models for mask synthesis
Granted: February 13, 2024
Patent Number:
11900042
In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
Energy efficient tag partitioning in cache memory
Granted: February 13, 2024
Patent Number:
11899586
A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the…
Energy efficient tag partitioning in cache memory
Granted: February 13, 2024
Patent Number:
11899586
A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the…
CFET SRAM cell utilizing 8 transistors
Granted: February 6, 2024
Patent Number:
11894049
A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS…
Global mistracking analysis in integrated circuit design
Granted: February 6, 2024
Patent Number:
11893332
For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.
Non-fighting level shifters
Granted: January 16, 2024
Patent Number:
11876516
A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.
Stochastic optical proximity corrections
Granted: January 16, 2024
Patent Number:
11874597
A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified…
Lightweight unified power format implementation for emulation and prototyping
Granted: January 9, 2024
Patent Number:
11868696
A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a…
System and method for optimizing emulation throughput by selective application of a clock pattern
Granted: January 9, 2024
Patent Number:
11868694
A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The…
Machine learning delay estimation for emulation systems
Granted: January 2, 2024
Patent Number:
11860227
A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and…
Deterministic data latency in serializer/deserializer-based design for test systems
Granted: January 2, 2024
Patent Number:
11860751
Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals.…
Skeleton representation of layouts for the development of lithographic masks
Granted: January 2, 2024
Patent Number:
11860531
In certain embodiments, a method includes the following steps. A layout used in a lithographic mask development process is accessed. For example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on the wafer. The layout includes a number of disjoint shapes. Skeleton representations for at least some of the disjoint shapes in the layout are determined. The skeleton representation of an individual shape has elements of two or more…
