Reducing spurious write operations in a memory device
Granted: April 8, 2025
Patent Number:
12272424
A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter…
Finding equivalent classes of hard defects in stacked MOSFET arrays
Granted: April 8, 2025
Patent Number:
12271668
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the…
Signal integrity monitoring system
Granted: April 8, 2025
Patent Number:
12270857
Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.
Built-in self-test circuit for row hammering in memory
Granted: April 1, 2025
Patent Number:
12266413
A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values…
Clock aware simulation vector processor
Granted: April 1, 2025
Patent Number:
12265779
A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of…
Inverse lithography and machine learning for mask synthesis
Granted: April 1, 2025
Patent Number:
12265325
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. These techniques include providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The techniques further include performing, using the ML Model, a plurality of dilated convolutions relating to the design pattern, and inferring, using the ML model, one or more masks for use in manufacturing the semiconductor device, based…
Memory profiler for emulation
Granted: April 1, 2025
Patent Number:
12265122
A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence…
Managing high performance simulation representation of an emulation system
Granted: March 25, 2025
Patent Number:
12259806
A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the…
Dynamic clock scaling using compression and serialization
Granted: March 25, 2025
Patent Number:
12259746
A method of transferring data from a first circuit block to a second circuit block, includes, in part, sampling the data using a first clock signal during a first cycle, compressing the sampled data at the first circuit block and using a compression ratio. In response to a determination that the compression ratio is equal to or less than a threshold value, selecting the compressed data for transmission to the second circuit block, and selecting a second clock signal for sampling the data…
Diagnosis of inconsistent constraints in a power intent for an integrated circuit design
Granted: March 18, 2025
Patent Number:
12254256
A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where…
Glitch identification and power analysis using simulation vectors
Granted: March 18, 2025
Patent Number:
12254255
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.
Multi-protocol analog front end circuit
Granted: March 11, 2025
Patent Number:
12249394
An apparatus for processing an input signal from a memory includes an attenuator circuit and an analog front end (AFE) circuit. The attenuator circuit attenuates the input signal from the memory to produce an attenuated signal. The AFE circuit includes a first amplification stage and a second amplification stage. The first amplification stage has an n-type metal-oxide semiconductor (NMOS) transistor. The NMOS transistor has a gate that receives the attenuated signal from the attenuator…
Large scale computational lithography using machine learning models
Granted: March 11, 2025
Patent Number:
12249115
A computational lithography process uses machine learning models. An aerial image produced by a lithographic mask is first calculated using a two-dimensional model of the lithographic mask. This first aerial image is applied to a first machine learning model, which infers a second aerial image. The first machine learning model was trained using a training set that includes aerial images calculated using a more accurate three-dimensional model of lithographic masks. The two-dimensional…
Poly-bit cells
Granted: March 11, 2025
Patent Number:
12248744
Poly-bit cells and methods for forming the same are provided. In one example, a method for forming a poly-bit cell includes identifying layouts in a library of single-bit cells having one or more of a different functionality and a different drive that are combinable; storing, in memory, layouts that are combinable; and creating layouts of poly-bit cells from the stored combinable single-bit cells. Each poly-bit cell combined from layouts of at least two single-bit cells has one or more…
Phase detection circuitry for high-frequency phase error detection
Granted: March 11, 2025
Patent Number:
12248335
Phase detector circuitry includes first mixer circuitry configured to receive a first clock signal and a second clock signal. The first mixer circuitry includes a first plurality of transistors. The first plurality of transistors includes first transistors, second transistors, and an output transistor. The first transistors receive the first clock signal, and the second transistors receive the second clock signal. The first output transistor outputs a first output signal. The first…
Enforcing mask synthesis consistency across random areas of integrated circuit chips
Granted: March 4, 2025
Patent Number:
12242183
A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties…
Method and system for transmission power control in bluetooth low energy controllers
Granted: March 4, 2025
Patent Number:
12245163
A method for dynamically adjusting transmit power of a first device that is in communication with a second device using a wireless communications protocol includes, in part, determining, by the second device, a received signal strength indication (RSSI) associated with a signal received from the first device; determining, by the second device, a first amount of power adjustment for the first device in accordance with the determined RSSI; transmitting the first amount of power adjustment…
Memory write assist
Granted: March 4, 2025
Patent Number:
12243585
An example described herein is a circuit including a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit and a capacitor. The dynamic CMOS inverter level translator circuit is electrically connected to a first power domain and has a first input node configured to receive a first trigger signal generated in the first power domain. The dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal…
Output driver level-shifting latch circuit for dual-rail memory
Granted: March 4, 2025
Patent Number:
12243581
A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power…
Data-driven clock port and clock signal recognition
Granted: March 4, 2025
Patent Number:
12242783
Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the…
