Unit magnification large-format catadioptric lens for microlithography
Granted: September 9, 2014
Patent Number:
8830590
A unit magnification Wynn-Dyson lens for microlithography has an image field sized to accommodate between four and six die of dimensions 26 mm×36 mm. The lens has a positive lens group that consists of either three or four refractive lens elements, with one of the lens elements being most mirror-wise and having a prism-wise concave aspheric surface. Protective windows respectively reside between object and image planes and the corresponding prism faces. The lens is corrected for at…
Programmable illuminator for a photolithography system
Granted: September 2, 2014
Patent Number:
8823921
A programmable illuminator for a photolithography system includes a light source, a first optical system having a light uniformizing element, a programmable micro-mirror device, and a second optical system that forms an illumination field that illuminates a reticle. The programmable micro-mirror device can be configured to perform shutter and edge-exposure-blocking functions that have previously required relatively large mechanical devices. Methods of improving illumination field…
Systems and methods for forming a time-averaged line image
Granted: September 2, 2014
Patent Number:
8822353
Systems and methods for forming a time-averaged line image having a relatively high amount of intensity uniformity along its length is disclosed. The method includes forming at an image plane a line image having a first amount of intensity non-uniformity in a long-axis direction and forming a secondary image that at least partially overlaps the primary image. The method also includes scanning the secondary image over at least a portion of the primary image and in the long-axis direction…
Systems for and methods of laser-enhanced plasma processing of semiconductor materials
Granted: August 5, 2014
Patent Number:
8796151
Systems for and methods of laser-enhanced plasma processing of semiconductor materials are disclosed. The method includes supporting a semiconductor material in a processing chamber interior and subjecting the semiconductor material to a plasma process. The method also includes simultaneously heating the wafer surface with a laser beam through a window in the processing chamber to increase the reaction rate of the plasma process. Other methods include performing laser heating of the…
Photolithographic LED fabrication using phase-shift mask
Granted: August 5, 2014
Patent Number:
8796053
Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure…
Optical alignment systems for forming LEDs having a rough surface
Granted: July 15, 2014
Patent Number:
8781213
An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the…
Methods of characterizing semiconductor light-emitting devices based on product wafer characteristics
Granted: July 1, 2014
Patent Number:
8765493
Methods of characterizing semiconductor light-emitting devices (LEDs) based on product wafer characteristics are disclosed. The methods include measuring at least one product wafer characteristic, such curvature or device layer stress. The method also includes establishing a relationship between the at least one characteristic and the emission wavelengths of the LED dies formed from the product wafer. The relationship allows for predicting the emission wavelength of LED structures formed…
Apparatus and method for improving the intensity profile of a beam image used to process a substrate
Granted: June 3, 2014
Patent Number:
8742286
Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell…
Through silicon via and method of fabricating same
Granted: May 27, 2014
Patent Number:
8735251
A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from…
Dual-loop control for laser annealing of semiconductor wafers
Granted: April 8, 2014
Patent Number:
8691598
Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that…
Solder interconnect pads with current spreading layers
Granted: March 11, 2014
Patent Number:
8669660
Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of…
Activating GaN LEDs by laser spike annealing and flash annealing
Granted: February 25, 2014
Patent Number:
8658451
Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer…
Through substrate via including variable sidewall profile
Granted: February 4, 2014
Patent Number:
8643190
A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively…
Through silicon via for use in integrated circuit chips
Granted: January 28, 2014
Patent Number:
8637937
A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from…
Laser spike annealing for GaN LEDs
Granted: November 26, 2013
Patent Number:
8592309
Methods of performing laser spike annealing (LSA) in forming gallium nitride (GaN) light-emitting diodes (LEDs) as well as GaN LEDs formed using LSA are disclosed. An exemplary method includes forming atop a substrate a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method also includes performing LSA by scanning a laser beam over the p-GaN layer. The method further includes forming a transparent conducting layer atop the GaN multilayer…
Underfill flow guide structures and method of using same
Granted: November 12, 2013
Patent Number:
8580673
Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.
Two-beam laser annealing with improved temperature performance
Granted: October 1, 2013
Patent Number:
8546805
Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings…
Electrical interconnect forming method
Granted: September 24, 2013
Patent Number:
8541299
An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder…
Thermo-compression bonded electrical interconnect structure and method
Granted: September 24, 2013
Patent Number:
8541291
An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder…
Laser annealing scanning methods with reduced annealing non-uniformities
Granted: August 6, 2013
Patent Number:
8501638
Laser annealing scanning methods that result in reduced annealing non-uniformities in semiconductor device structures under fabrication are disclosed. The methods include defining a length of an annealing laser beam such that the tails of the laser beam resided only within scribe lines that separate the semiconductor device structures. The annealing laser beam tails from adjacent scan path segments can overlap or not overlap within the scribe lines. The cross-scan length of the annealing…
