Compiler-based generation of transaction accurate models from high-level languages
Granted: July 9, 2024
Patent Number:
12032932
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that…
Systems and methods to extract beamforming parameters at a radio unit (RU) of a radio access network (RAN)
Granted: July 2, 2024
Patent Number:
12028137
Embodiments herein describe a radio unit (RU) of a radio access network (RAN), that extracts payload data and beamforming parameters from matrices received from a base station based on format parameters of the matrices and format parameters of channel state information resource signal resource elements (CSI-RS REs). The matrices include a payload matrix and first and second bit mask matrices. Locations of CSI-RS REs are determined based on the bit mask matrices. The payload matrix is…
Fanout integration for stacked silicon package assembly
Granted: July 2, 2024
Patent Number:
12027493
A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound…
Dynamic port handling for isolated modules and dynamic function exchange
Granted: July 2, 2024
Patent Number:
12026444
Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s)…
Impactless firmware update
Granted: June 25, 2024
Patent Number:
12020021
Techniques to update firmware without a system reset include preserving state information associated with one or more firmware services, suspending processing of firmware service requests, loading an updated firmware image, and resuming processing of firmware service requests based on the preserved state information and the updated firmware image. Unpreserved states of one or more other firmware services may be recreated upon resumption of processing of the firmware service requests.
Optimizing use of computer resources in implementing circuit designs through machine learning
Granted: June 25, 2024
Patent Number:
12019964
Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in…
Dynamically allocated buffer pooling
Granted: June 25, 2024
Patent Number:
12019908
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further…
Systems and methods to transport memory mapped traffic amongst integrated circuit devices
Granted: June 25, 2024
Patent Number:
12019576
Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC…
Lock-stepping asynchronous logic
Granted: June 25, 2024
Patent Number:
12019526
Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the…
Switched capacitor circuitry for mitigating pole-zero doublet errors in an analog circuit
Granted: June 18, 2024
Patent Number:
12015419
Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution…
High-throughput regular expression processing using an integrated circuit
Granted: June 18, 2024
Patent Number:
12014072
A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating…
Antenna test system and a method for testing an antenna
Granted: June 18, 2024
Patent Number:
12013424
An antenna test system for testing an antenna with a plurality of antenna elements is disclosed. The antenna test system includes an antenna element connector for every antenna element of the antenna, wherein the antenna element connectors are wiredly couplable to the respective antenna elements, a channel emulator comprising an antenna port for every antenna element connector and a number of test signal ports, and a signal evaluation device for every one of the test signal ports that is…
Multi-die integrated circuit with data processing engine array
Granted: June 4, 2024
Patent Number:
12001367
An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die…
Zoned accelerator embedded processing
Granted: May 28, 2024
Patent Number:
11995021
Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead…
Dataflow-based computer program visualization and refactoring
Granted: May 21, 2024
Patent Number:
11989537
A computer-based visualization and refactoring system is capable of analyzing a computer program to determine computation tasks of the computer program and channels linking the computation tasks. The system generates, in a memory of computer hardware, a dataflow graph having nodes representing the computation tasks and edges representing the channels. The edges connect the nodes. Source code representations of the computation tasks are determined. Execution metrics of the computer…
Fine-grained multi-tenant cache management
Granted: May 14, 2024
Patent Number:
11983117
The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus,…
Arbitration of commands between non-volatile memory storage and remote hosts
Granted: May 14, 2024
Patent Number:
11983441
An integrated circuit includes a front-end interface, a back-end interface, a controller, and arbiter circuitry. The front-end interface communicates with a remote host over a front-end fabric. The back-end interface communicates with nonvolatile memory (NVM) subsystems over a back-end fabric. The controller is coupled between the front-end interface and the back-end interface. The controller receives commands from the remote host for the NVM subsystems, and stores the commands in queue…
Adaptive acceleration of transport layer security
Granted: May 14, 2024
Patent Number:
11983264
Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain…
Adaptive integrated programmable data processing unit
Granted: May 14, 2024
Patent Number:
11983133
An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function…
High-throughput regular expression processing with path priorities using an integrated circuit
Granted: May 14, 2024
Patent Number:
11983122
A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a…
