Multi dimensional memory compression using bytewide write enable
Granted: August 24, 2021
Patent Number:
11100267
Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input…
Accelerating algorithms and applications on FPGAs
Granted: August 24, 2021
Patent Number:
11099918
A method for accelerating algorithms and applications on field-programmable gate arrays (FPGAs). The method includes: obtaining, from a host application, by a run-time configurable kernel, implemented on an FPGA, a first set of kernel input data; obtaining, from the host application, by the run-time configurable kernel, a first set of kernel operation parameters; parameterizing the run-time configurable kernel at run-time, using the first set of kernel operation parameters; and…
Using receive timestamps to update latency estimates
Granted: August 17, 2021
Patent Number:
11095515
A data processing system comprising: first and second network ports each operable to support a network connection configured according to one or more of a predetermined set of physical layer protocols; and a processor configured to, on a network message being formed for transmission to a network endpoint accessible over either of the first and second network ports: estimate the total time required to, for each of the predetermined set of physical layer protocols, negotiate a respective…
Delegated snoop protocol
Granted: August 17, 2021
Patent Number:
11093394
An example Cache-Coherent Non-Uniform Memory Access (CC-NUMA) system includes: one or more fabric switches; a home agent coupled to the one or more fabric switches; first and second response agents coupled to the fabric switches; wherein the home agent is configured to send a delegated snoop message to the first response agent, the delegated snoop message instructing the first response agent to snoop the second response agent; wherein the first response agent is configured to snoop the…
Data processing system
Granted: August 17, 2021
Patent Number:
11093284
A data processing system has a poll mode driver and a library supporting protocol processing. The poll mode driver and the library are non-operating system functionalities. An application is provided. An operation system is configured while executing in kernel mode and in response to the application being determined to be unresponsive, use a helper process being an operating system functionality executing at user-mode to cause a receive or transmit mode of the application to continue.
High parallelism computing system and instruction scheduling method thereof
Granted: August 17, 2021
Patent Number:
11093225
A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially…
Removing blocking artifacts in video encoders
Granted: August 10, 2021
Patent Number:
11089308
A method for video encoding is provided. The method comprises retrieving a first video frame comprising a plurality of pixel blocks; determining a rate distortion optimization (RDO) cost for a first prediction mode for a pixel block; determining a variance-bits ratio (VBR) of the pixel block; upon determining the VBR is greater than a predefined threshold, scaling the RDO cost for the first prediction mode based on a predefined scale factor; and selecting one of the first prediction mode…
Pulsed flip-flop capable of being implemented across multiple voltage domains
Granted: August 10, 2021
Patent Number:
11088678
Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit…
Supporting access to accelerators on a programmable integrated circuit by multiple host processes
Granted: August 10, 2021
Patent Number:
11086815
Supporting multiple clients on a single programmable integrated circuit (IC) can include implementing a first image within the programmable IC in response to a first request for processing to be performed by the programmable IC, wherein the request is from a first process executing in a host data processing system coupled to the programmable IC, receiving, using a processor of the host data processing system, a second request for processing to be performed on the programmable IC from a…
Network interface device
Granted: August 3, 2021
Patent Number:
11082364
A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.
System and method for determining bit types for polar encoding and decoding
Granted: August 3, 2021
Patent Number:
11082067
Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a…
Sub-matrix reduction for quasi-cyclic LDPC codes
Granted: July 27, 2021
Patent Number:
11075650
A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code. The first codeword includes a sequence of data arranged according to an order of columns in a first parity-check matrix associated with the QC LDPC code. A codeword reordering stage generates a reordered codeword by changing the sequence of the data in the first codeword based at least in part on a size of one or more circulant submatrices in the first…
Die singulation and stacked device structures
Granted: July 27, 2021
Patent Number:
11075117
Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device…
Routing network using global address map with adaptive main memory expansion for a plurality of home agents
Granted: July 27, 2021
Patent Number:
11074208
An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple…
Test vehicle for package testing
Granted: July 27, 2021
Patent Number:
11073550
A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.
Adaptive integrated programmable device platform
Granted: July 13, 2021
Patent Number:
11063594
An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can…
Data selection network for a data processing engine in an integrated circuit
Granted: July 13, 2021
Patent Number:
11061673
An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute…
Test circuits for testing a die stack
Granted: July 6, 2021
Patent Number:
11054461
Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test…
Functional coverage of designs using transition bins and cross coverage
Granted: July 6, 2021
Patent Number:
11055458
Verification for a design can include, for a covergroup corresponding to a variable of the design, generating a state coverage data structure specifying a plurality of transition bins. Each transition bin can include a sequence. Each sequence can specify states of the variable to be traversed in order during simulation of the design. Verification can include generating a state sequence table configured to use state values as keys and one or more of the sequences as data for the…
Bootstrapping a programmable integrated circuit based network interface card
Granted: July 6, 2021
Patent Number:
11055106
Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A…
