Intra-estimation for high performance video encoders
Granted: June 22, 2021
Patent Number:
11044484
An example method of encoding a video includes selecting blocks of pixels in a frame of the video, the blocks having luminance (Y) blocks, red color difference (Cr) blocks, and blue color difference (Cb) blocks; performing intra-estimation based on reconstructed pixels of at the blocks of pixels to generate predicted blocks and then subtracting the predicted blocks from the blocks of pixels to generate residual data, the residual data comprising respective residual data for the Y-blocks…
Network interface device
Granted: June 22, 2021
Patent Number:
11044183
A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.
Method and apparatus of package enabled ESD protection
Granted: June 22, 2021
Patent Number:
11043484
Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the…
Forming and/or configuring stacked dies
Granted: June 22, 2021
Patent Number:
11043480
Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two…
Inductor design in active 3D stacking technology
Granted: June 22, 2021
Patent Number:
11043470
Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of…
Power distribution for active-on-active die stack with reduced resistance
Granted: June 22, 2021
Patent Number:
11041211
Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack…
Transaction associations in waveform displays
Granted: June 22, 2021
Patent Number:
11042564
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal…
Enabling integrity and authenticity of design data
Granted: June 22, 2021
Patent Number:
11042610
Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation.…
Low offset and enhanced write margin for stacked fabric dies
Granted: June 22, 2021
Patent Number:
11043263
A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is…
Method and system for correlation of a behavioral model to a circuit realization for a communications system
Granted: June 15, 2021
Patent Number:
11038768
A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse…
Software-defined buffer/transposer for general matrix multiplication in a programmable IC
Granted: June 15, 2021
Patent Number:
11036827
Methods and apparatus are described for simultaneously buffering and reformatting (e.g., transposing) a matrix for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). Examples of the present disclosure increase the effective double data rate (DDR) memory throughput for streaming data into GEMM digital signal processing (DSP) engine multifold, as well as eliminate slow data reformatting on a host central…
Multi-threaded shared memory functional simulation of dataflow graph
Granted: June 15, 2021
Patent Number:
11036546
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges. A compiler converts the source code into a bit stream and/or object code which configures a heterogeneous processing environment of a SoC to execute the graph. Before implementing the dataflow graph on the SoC, the programmer…
Integration of a programmable device and a processing system in an integrated circuit package
Granted: June 1, 2021
Patent Number:
11024583
An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one…
Programmed input/output mode
Granted: June 1, 2021
Patent Number:
11023411
A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured…
Optical communication circuits
Granted: May 25, 2021
Patent Number:
11018772
Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes multiple lasers that input an electronic signal. Each laser encodes and outputs a respective optical data signal based on the electronic signal. Each laser has a different configuration of one or more first optical parameters. A first selection circuit selects the respective optical data signal from one of the lasers. Multiple optical components…
Method to mitigate signal feed through ESD elements
Granted: May 25, 2021
Patent Number:
11018130
An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the…
Yield-centric power gated regulated supply design with programmable leakers
Granted: May 25, 2021
Patent Number:
11017822
Examples described herein provide a method for disabling a defective portion of a fabric die of a stacked IC device. The method includes receiving a signal indicating that a portion of a fabric die of a stacked IC device including at least two fabric dies is defective. The method further includes, in response to the signal, pulling a source voltage rail of the defective portion to ground, thereby disabling the portion, and operating the remainder of the fabric die without interference…
Cascade streaming between data processing engines in an array
Granted: May 25, 2021
Patent Number:
11016822
Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data…
NOC peripheral interconnect interrogation scheme
Granted: May 18, 2021
Patent Number:
11010322
A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the…
Phase noise compensation in digital beamforming radar systems
Granted: May 18, 2021
Patent Number:
11009597
A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of…
