INJECTION CONTROL IN SEMICONDUCTOR POWER DEVICES
Granted: December 3, 2015
Application Number:
20150349101
Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first…
HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS DELIMITED BY NITRIDE-CAPPED TRENCH GATE STACKS AND METHOD
Granted: November 26, 2015
Application Number:
20150340363
A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to…
EMBEDDED PACKAGE AND METHOD THEREOF
Granted: November 12, 2015
Application Number:
20150325559
The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to…
ULTRA-THIN SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
Granted: November 12, 2015
Application Number:
20150325500
A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of…
SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS
Granted: October 29, 2015
Application Number:
20150311295
Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top…
MOSFET SWITCH CIRCUIT FOR SLOW SWITCHING APPLICATION
Granted: October 15, 2015
Application Number:
20150295495
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first…
CLOSED CELL LATERAL MOSFET USING SILICIDE SOURCE AND BODY REGIONS
Granted: October 8, 2015
Application Number:
20150287820
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the…
ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS
Granted: September 24, 2015
Application Number:
20150270383
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
FLOATING GUARD RING FOR HV INTERCONNECT
Granted: August 6, 2015
Application Number:
20150221720
Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the…
CHARGE RESERVOIR IGBT TOP STRUCTURE
Granted: May 21, 2015
Application Number:
20150137175
An IGBT device includes one or more trench gates disposed over a semiconductor substrate and a floating body region of the first conductivity type disposed between two neighboring trench gates and between a semiconductor substrate and a heavily doped top region of the second conductivity type. A body region of the first conductivity type disposed over the top region has a doping concentration higher than that of the floating body region of the first conductivity type. It is emphasized…
METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET
Granted: May 14, 2015
Application Number:
20150129956
Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with…
DUAL TRENCH-GATE IGBT STRUCTURE
Granted: February 5, 2015
Application Number:
20150035003
Aspects of the present disclosure describe an IGBT device including a substrate including a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and…
NORMALLY ON HIGH VOLTAGE SWITCH
Granted: January 22, 2015
Application Number:
20150021682
In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to…
THROUGH SILICON VIA PROCESSING METHOD FOR LATERAL DOUBLE-DIFFUSED MOSFETS
Granted: December 4, 2014
Application Number:
20140357038
The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed…
NANOTUBE SEMICONDUCTOR DEVICES
Granted: October 9, 2014
Application Number:
20140299914
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on…
SHIELDED GATE TRENCH MOSFET PACKAGE
Granted: September 18, 2014
Application Number:
20140264571
A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically…
FAULT TOLERANT POWER SUPPLY INCORPORATING INTELLIGENT LOAD SWITCH TO PROVIDE UNINTERRUPTED POWER
Granted: September 18, 2014
Application Number:
20140277802
A fault tolerant power supply system includes at least one load switch circuit configured to connect, using a main switch, an input voltage to an output node of the load switch circuit when the load switch circuit is turned on and at least one power channel coupled to the load switch circuit to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is…
METHOD FOR FORMING TERMINATION STRUCTURE FOR GALLIUM NITRIDE SCHOTTKY DIODE
Granted: September 18, 2014
Application Number:
20140273417
A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer…
ACTIVE ESD PROTECTION CIRCUIT
Granted: September 18, 2014
Application Number:
20140268441
A high-voltage gate driver circuit configured to drive a high-side power switch and a low-side power switch includes an active dv/dt triggered ESD protection circuit coupled between a protected node and a power rail node. The active dv/dt triggered ESD protection circuit includes a dv/dt circuit controlling an ESD protection transistor connected between the protected node and the power rail node. The ESD protection transistor is turned on when an ESD event occurs at the protected node to…
SWITCHING REGULATOR WITH ADAPTIVE PWM/PFM MODULATOR
Granted: September 18, 2014
Application Number:
20140266090
A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single…
