ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS
Granted: September 24, 2015
Application Number:
20150270383
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
FLOATING GUARD RING FOR HV INTERCONNECT
Granted: August 6, 2015
Application Number:
20150221720
Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the…
CHARGE RESERVOIR IGBT TOP STRUCTURE
Granted: May 21, 2015
Application Number:
20150137175
An IGBT device includes one or more trench gates disposed over a semiconductor substrate and a floating body region of the first conductivity type disposed between two neighboring trench gates and between a semiconductor substrate and a heavily doped top region of the second conductivity type. A body region of the first conductivity type disposed over the top region has a doping concentration higher than that of the floating body region of the first conductivity type. It is emphasized…
METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET
Granted: May 14, 2015
Application Number:
20150129956
Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with…
DUAL TRENCH-GATE IGBT STRUCTURE
Granted: February 5, 2015
Application Number:
20150035003
Aspects of the present disclosure describe an IGBT device including a substrate including a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and…
NORMALLY ON HIGH VOLTAGE SWITCH
Granted: January 22, 2015
Application Number:
20150021682
In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to…
THROUGH SILICON VIA PROCESSING METHOD FOR LATERAL DOUBLE-DIFFUSED MOSFETS
Granted: December 4, 2014
Application Number:
20140357038
The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed…
NANOTUBE SEMICONDUCTOR DEVICES
Granted: October 9, 2014
Application Number:
20140299914
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on…
METHOD FOR FORMING TERMINATION STRUCTURE FOR GALLIUM NITRIDE SCHOTTKY DIODE
Granted: September 18, 2014
Application Number:
20140273417
A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer…
FAULT TOLERANT POWER SUPPLY INCORPORATING INTELLIGENT LOAD SWITCH TO PROVIDE UNINTERRUPTED POWER
Granted: September 18, 2014
Application Number:
20140277802
A fault tolerant power supply system includes at least one load switch circuit configured to connect, using a main switch, an input voltage to an output node of the load switch circuit when the load switch circuit is turned on and at least one power channel coupled to the load switch circuit to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is…
FAULT TOLERANT POWER SUPPLY INCORPORATING INTELLIGENT GATE DRIVER-SWITCH CIRCUIT TO PROVIDE UNINTERRUPTED POWER
Granted: September 18, 2014
Application Number:
20140268939
A fault tolerant power supply system includes at least one load switch configured to connect an input voltage to an output node of the load switch when the load switch is turned on and at least one power channel coupled to the load switch to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the…
ACTIVE ESD PROTECTION CIRCUIT
Granted: September 18, 2014
Application Number:
20140268441
A high-voltage gate driver circuit configured to drive a high-side power switch and a low-side power switch includes an active dv/dt triggered ESD protection circuit coupled between a protected node and a power rail node. The active dv/dt triggered ESD protection circuit includes a dv/dt circuit controlling an ESD protection transistor connected between the protected node and the power rail node. The ESD protection transistor is turned on when an ESD event occurs at the protected node to…
SWITCHING REGULATOR WITH ADAPTIVE PWM/PFM MODULATOR
Granted: September 18, 2014
Application Number:
20140266090
A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single…
SHIELDED GATE TRENCH MOSFET PACKAGE
Granted: September 18, 2014
Application Number:
20140264571
A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically…
VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE
Granted: September 11, 2014
Application Number:
20140252372
A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction…
HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD
Granted: August 28, 2014
Application Number:
20140239382
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be…
METHOD FOR PREPARING SEMICONDUCTOR DEVICES APPLIED IN FLIP CHIP TECHNOLOGY
Granted: August 28, 2014
Application Number:
20140242756
A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface…
HIGH VOLTAGE FAST RECOVERY TRENCH DIODE
Granted: August 28, 2014
Application Number:
20140239436
Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating…
TERMINATION TRENCH FOR POWER MOSFET APPLICATIONS
Granted: August 28, 2014
Application Number:
20140239388
Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will…
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
Granted: August 28, 2014
Application Number:
20140239383
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
