Method of Making MOSFET Integrated with Schottky Diode with Simplified One-time Top-Contact Trench Etching
Granted: August 21, 2014
Application Number:
20140235024
Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and…
UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS)
Granted: August 21, 2014
Application Number:
20140231963
A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
SEMICONDUCTOR DEVICE EMPLOYING TRENCHES FOR ACTIVE GATE AND ISOLATION
Granted: August 14, 2014
Application Number:
20140225190
A semiconductor device with multiple transistor devices includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device being an LDMOS transistor formed in the semiconductor layer between the first trench and the second trench; and a second…
SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
Granted: August 14, 2014
Application Number:
20140225188
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an…
METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE
Granted: August 14, 2014
Application Number:
20140225185
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base…
POWER FACTOR CORRECTION DEVICE AND CORRECTING METHOD THEREOF
Granted: August 7, 2014
Application Number:
20140218990
A power factor correction device comprises a power stage circuit converting input alternating current voltage into input current according to a pulse width modulation signal and outputs the input current to a load generating output voltage on the load, and sampling the input current outputting a correcting current; a current compensating circuit receiving and comparing the correcting current with a reference current signal generating a compensating current signal; a voltage compensating…
TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE
Granted: July 10, 2014
Application Number:
20140193958
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…
VERTICAL DMOS TRANSISTOR
Granted: June 19, 2014
Application Number:
20140167144
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench…
Method for Top-side Cooled Semiconductor Package with Stacked Interconnection Plates
Granted: June 5, 2014
Application Number:
20140154843
A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a…
OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS
Granted: May 22, 2014
Application Number:
20140138767
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and…
LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE
Granted: May 15, 2014
Application Number:
20140134825
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second…
FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT
Granted: May 15, 2014
Application Number:
20140134813
Fabricating a semiconductor device includes: forming a gate trench on a semiconductor substrate; forming a spacer inside the gate trench; forming one or more gate electrodes within the gate trench; implanting a body region; implanting a source region; forming a contact trench; disposing dielectric material within the gate trench; removing at least a portion of the dielectric material such that at least a portion of the source region extends above the dielectric material; and depositing a…
Dual-leadframe Multi-chip Package
Granted: April 17, 2014
Application Number:
20140103512
A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional…
MOSFET DEVICE AND FABRICATION
Granted: April 3, 2014
Application Number:
20140091386
A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.
Active Clamp Protection Circuit For Power Semiconductor Device For High Frequency Switching
Granted: March 27, 2014
Application Number:
20140085760
A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct…
Semiconductor Packaging Method Using Connecting Plate for Internal Connection
Granted: March 20, 2014
Application Number:
20140080263
A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding…
METHOD FOR FORMING A SCHOTTKY BARRIER DIODE INTEGRATED WITH A TRENCH MOSFET
Granted: March 13, 2014
Application Number:
20140073098
A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches…
Semiconductor Package with Connecting Plate for Internal Connection
Granted: March 13, 2014
Application Number:
20140070386
A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding…
MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE
Granted: February 27, 2014
Application Number:
20140054687
A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact…
STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS
Granted: February 27, 2014
Application Number:
20140054758
The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
