Three-Dimensional High Voltage Gate Driver Integrated Circuit
Granted: February 20, 2014
Application Number:
20140049293
A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage…
LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT
Granted: February 20, 2014
Application Number:
20140048880
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules…
SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE
Granted: February 20, 2014
Application Number:
20140048846
Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator…
NANOTUBE SEMICONDUCTOR DEVICES
Granted: February 13, 2014
Application Number:
20140042490
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.
Top Exposed Semiconductor Chip Package
Granted: February 6, 2014
Application Number:
20140035116
A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.
HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM)
Granted: January 30, 2014
Application Number:
20140027841
A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried…
TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE
Granted: January 30, 2014
Application Number:
20140027840
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…
CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
Granted: January 30, 2014
Application Number:
20140027819
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform…
METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS
Granted: December 26, 2013
Application Number:
20130341689
Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and…
INTEGRATED SNUBBER IN A SINGLE POLY MOSFET
Granted: December 19, 2013
Application Number:
20130334599
A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more…
INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET
Granted: November 21, 2013
Application Number:
20130309823
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in…
SEMICONDUCTOR ENCAPSULATION METHOD
Granted: November 21, 2013
Application Number:
20130309816
A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one…
METHOD OF FORMING AN ASSYMETRIC POLY GATE FOR OPTIMUM TERMINATION DESIGN IN TRENCH POWER MOSFETS
Granted: September 5, 2013
Application Number:
20130228857
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER
Granted: August 8, 2013
Application Number:
20130203225
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region…
FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE
Granted: August 8, 2013
Application Number:
20130203224
Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode…
OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS
Granted: May 23, 2013
Application Number:
20130126966
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can…
DUAL CHANNEL TRENCH LDMOS TRANSISTORS AND TRANSISTORS INTEGRATED THEREWITH
Granted: May 16, 2013
Application Number:
20130119465
A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body…
Termination Structure for Gallium Nitride Schottky Diode
Granted: May 16, 2013
Application Number:
20130119394
A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer…
Vertical Gallium Nitride Schottky Diode
Granted: May 16, 2013
Application Number:
20130119393
A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction…
TWO-DIMENSIONAL SHIELDED GATE TRANSISTOR DEVICE AND METHOD OF MANUFACTURE
Granted: May 2, 2013
Application Number:
20130105886
A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The…
