Semiconductor device integrating high and low voltage devices
Granted: December 18, 2018
Patent Number:
10157984
The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of…
High surge bi-directional transient voltage suppressor
Granted: December 18, 2018
Patent Number:
10157904
A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The…
Pulse transformer
Granted: December 18, 2018
Patent Number:
10157702
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
Low capacitance transient voltage suppressor
Granted: November 27, 2018
Patent Number:
10141300
A transient voltage suppressor (TVS) circuit includes a P-N junction diode and a silicon controlled rectifier (SCR) formed integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes multiple fingers of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer, defining current conducting regions between the fingers. The current paths for the SCR and the P-N junction diode are formed in each…
Method and structure for wafer level packaging with large contact area
Granted: November 27, 2018
Patent Number:
10141264
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
Molded intelligent power module and method of making the same
Granted: November 27, 2018
Patent Number:
10141249
An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom…
Nano-tube MOSFET technology and devices
Granted: November 6, 2018
Patent Number:
10121857
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of…
Method of forming closed cell lateral MOSFET using silicide source
Granted: November 6, 2018
Patent Number:
10121668
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body…
Process method and structure for high voltage MOSFETs
Granted: October 30, 2018
Patent Number:
10115814
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant…
JFET and LDMOS transistor formed using deep diffusion regions
Granted: October 23, 2018
Patent Number:
10109625
A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant…
Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode
Granted: October 16, 2018
Patent Number:
10103240
A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column…
Switch circuit with controllable phase node ringing
Granted: October 16, 2018
Patent Number:
10103140
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second…
TVS structures for high surge and low capacitance
Granted: October 9, 2018
Patent Number:
10096588
A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer…
MOS device with island region
Granted: September 11, 2018
Patent Number:
10074742
A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded…
Termination design for high voltage device
Granted: September 4, 2018
Patent Number:
10069005
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…
Full-time inductor current monitoring method by sensing low side switch
Granted: August 28, 2018
Patent Number:
10063146
Aspects of the present disclosure describe a SMPS system, comprising a SMPS and an inductor current sensing device. The SMPS comprise a high-side (HS) switch and a low-side (LS) switch coupled in series and an output filter including an inductor and a capacitor coupled to a switch node formed by the HS and LS switches. An inductor current is supplied by the inductor to a load. The inductor current sensing device coupled across the LS switch has a first input configured to receive a node…
Nanotube termination structure for power semiconductor devices
Granted: August 28, 2018
Patent Number:
10062755
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the…
Variable snubber for MOSFET application
Granted: August 28, 2018
Patent Number:
10062685
Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.
Low capacitance bidirectional transient voltage suppressor
Granted: August 28, 2018
Patent Number:
10062682
A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and…
Composite masking self-aligned trench MOSFET
Granted: August 21, 2018
Patent Number:
10056461
Aspects of the present disclosure discloses a method for fabricating a trench MOSFET device comprising simultaneously forming a narrow trench and a wide trench into a semiconductor substrate using a mask to defines the narrow trench and the wide trench, forming an insulating layer over the semiconductor substrate with a first portion that fills up the narrow trench and a second portion that partially fills the wide trench, removing the second portion from the wide trench completely and…
