Method of manufacturing LV/MV super junction trench power MOSFETs
Granted: April 16, 2019
Patent Number:
10263070
Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a…
Forming switch circuit with controllable phase node ringing
Granted: April 9, 2019
Patent Number:
10256236
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second…
Forced zero voltage switching flyback converter
Granted: April 2, 2019
Patent Number:
10250152
A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding…
Over voltage protection for cascode switching power device
Granted: March 26, 2019
Patent Number:
10243551
Aspects of the present disclosure disclose a power semiconductor device coupled to a load operable to draw a load current comprising a power switch having a first terminal coupled to the load and a controller coupled to a control terminal of the power switch. The controller comprises a gate driving circuit configured to provide control of the control terminal of the power switch during normal switching operations; an overvoltage detection circuit configured to detect an overvoltage event…
Self-stabilized constant on-time control
Granted: March 26, 2019
Patent Number:
10243465
Some apparatus and associated methods relate to a buck-derived switched mode power supply with constant on-time and configured to substantially maintain a steady-state average switch period in a time interval between a start of a load transient and the time when the inductor current returns to a steady state. In an illustrative example, the time interval may include a first and a second predetermined number of cycles after the start of the load transient. The switch period may be…
Multifunction three quarter bridge
Granted: March 26, 2019
Patent Number:
10243449
Some apparatus and associated methods relate to a buck-derived switched mode power supply with three-quarter bridge (TQB) formed with a bypass switch in parallel with an inductor. In an illustrative example, the bypass switch may be configured to, in response to a decrease in average load demand, operate in a first mode to turn on the bypass switch to selectively circulate inductor current through the bypass switch while a high-side switch and a low-side switch are off. In a second mode,…
Method for forming a lateral super-junction MOSFET device and termination structure
Granted: March 26, 2019
Patent Number:
10243072
A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second…
Wafer level chip scale package structure and manufacturing method thereof
Granted: March 26, 2019
Patent Number:
10242926
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing…
Lateral PNP bipolar transistor with narrow trench emitter
Granted: March 5, 2019
Patent Number:
10224411
A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation…
Switched-mode ripple optimization
Granted: March 5, 2019
Patent Number:
10224805
Methods and apparatus relate to a minimizing ripple in a polyphase power supply by modulating a voltage pre-regulator output setpoint to minimize ripple performance. In an illustrative example, the modulation may include incrementally adjusting the pre-regulator output setpoint supplied, for example, to a multiphase controller. Some examples may reverse the increment direction in response to determining that the prior incremental adjustment yielded increased ripple. Each phase of the…
Scalable SGT structure with improved FOM
Granted: February 19, 2019
Patent Number:
10211333
A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer…
High surge transient voltage suppressor
Granted: February 19, 2019
Patent Number:
10211199
A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize…
Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
Granted: February 12, 2019
Patent Number:
10205017
A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer…
Folded channel trench MOSFET
Granted: February 5, 2019
Patent Number:
10199492
A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
Dual-gate trench IGBT with buried floating P-type shield
Granted: February 5, 2019
Patent Number:
10199455
A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate;…
Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
Granted: January 29, 2019
Patent Number:
10192982
A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped…
Integrated Schottky diode in high voltage semiconductor device
Granted: January 8, 2019
Patent Number:
10177221
This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide…
Molded intelligent power module
Granted: January 8, 2019
Patent Number:
10177080
An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth…
Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method
Granted: January 1, 2019
Patent Number:
10170559
An RC-IGBT includes a semiconductor body formed having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only…
Gallium nitride semiconductor device with improved termination scheme
Granted: January 1, 2019
Patent Number:
10170563
This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
