Device structure and manufacturing method using HDP deposited source-body implant block
Granted: May 5, 2015
Patent Number:
9024378
This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness…
Nano-tube MOSFET technology and devices
Granted: May 5, 2015
Patent Number:
9024375
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of…
Active clamp protection circuit for power semiconductor device for high frequency switching
Granted: April 21, 2015
Patent Number:
9013848
A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct…
Thin power device and preparation method thereof
Granted: April 14, 2015
Patent Number:
9006901
A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached…
Stacked multi-chip packaging structure and manufacturing method thereof
Granted: April 14, 2015
Patent Number:
9006870
A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding…
Vertical DMOS transistor
Granted: April 14, 2015
Patent Number:
9006820
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench…
Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching
Granted: April 14, 2015
Patent Number:
9006053
Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and…
Fabrication of trench DMOS device having thick bottom shielding oxide
Granted: April 7, 2015
Patent Number:
9000514
Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench…
Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage
Granted: April 7, 2015
Patent Number:
9000481
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second…
Vertical gallium nitride Schottky diode
Granted: March 31, 2015
Patent Number:
8994140
A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction…
Shielded gate trench MOS with improved source pickup layout
Granted: March 31, 2015
Patent Number:
8994101
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third…
Substrateless power device packages
Granted: March 24, 2015
Patent Number:
8987878
A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
LDMOS with accumulation enhancement implant
Granted: March 24, 2015
Patent Number:
8987821
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules…
Packaged power semiconductor with interconnection of dies and metal clips on lead frame
Granted: March 17, 2015
Patent Number:
8981539
A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
Wafer level chip scale package and process of manufacture
Granted: March 17, 2015
Patent Number:
8981464
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
Granted: March 17, 2015
Patent Number:
8981425
A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied…
Self aligned trench MOSFET with integrated diode
Granted: March 17, 2015
Patent Number:
8980716
Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator…
Corner layout for superjunction device
Granted: March 10, 2015
Patent Number:
8975720
A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first…
Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage
Granted: March 3, 2015
Patent Number:
8969950
A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned…
Method of forming a self-aligned charge balanced power DMOS
Granted: March 3, 2015
Patent Number:
8969953
Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and…
