SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASSEMBLIES
Granted: December 28, 2023
Application Number:
20230420351
In order to relieve the stress on the substrates in a 3D stacked electronic assembly, a substrate frame may be divided into a plurality of frame sections that are separated by spaces between the frame sections. These separations allow the substrates to expand/contract in response to temperature variations and other environmental conditions, and generally allow the substrates to move in one or more axial directions. The separations between the substrate portions may be design-specific for…
PROCESSING CHAMBER WITH ANNEALING MINI-ENVIRONMENT
Granted: December 28, 2023
Application Number:
20230420275
Apparatus and methods to process one or more wafers are described. The apparatus comprises a chamber defining an upper interior region and a lower interior region. A heater assembly is on the bottom of the chamber body in the lower interior region and defines a process region. A wafer cassette assembly is inside the heater assembly and a motor is configured to move the wafer cassette assembly from the lower process region inside the heater assembly to the upper interior region.
INTEGRATED METHOD AND TOOL FOR HIGH QUALITY SELECTIVE SILICON NITRIDE DEPOSITION
Granted: December 28, 2023
Application Number:
20230420232
Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying…
OPTICAL INSPECTION USING CONTROLLED ILLUMINATION AND COLLECTION POLARIZATION
Granted: December 28, 2023
Application Number:
20230417683
An optical inspection system, including (a) an illumination optics that is configured to generate an illumination light beam and to illuminate a sample with the illumination light beam; (b) at least one collection optics configured to collect light from the sample as a result of an impingement of the illumination light beam on the sample; (c) at least one detector configured to detect at least one detected light beam outputted from the at least one collection optics; (d) multiple…
ATOMIC LAYER DEPOSITION USING NOVEL OXYGEN-CONTAINING PRECURSORS
Granted: December 28, 2023
Application Number:
20230416915
Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The first precursor may include a first metal. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a metal oxide material on the substrate. The methods may include providing a second precursor to the…
SELF-ADJUSTABLE VARIABLE ORIFICE CHECK VALVE FOR BACK PRESSURE REDUCTION
Granted: December 21, 2023
Application Number:
20230407981
Variable orifice check valves comprising a flange with a guide pin, spring and movable plate are described. The flange has a body with at least one guide pin opening in the top surface. A guide pin is positioned within the at least one guide pin opening and a spring is positioned around the guide pin. The movable plate has an opening and slides along the guide pins with the spring between the top surface of the flange body and the bottom surface of the movable plate.
EPITAXIAL SILICON CHANNEL GROWTH
Granted: December 21, 2023
Application Number:
20230413569
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the…
PROFILE SHAPING FOR CONTROL GATE RECESSES
Granted: December 21, 2023
Application Number:
20230411462
Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing…
MODEL-BASED PARAMETER ADJUSTMENTS FOR DEPOSITION PROCESSES
Granted: December 21, 2023
Application Number:
20230411222
A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer and a chemical tank that provides liquid to the processing station during a deposition process. The chemical tank may provide measurements of characteristics of the liquid to a controller. The controller may be configured to receive the measurements from the chemical tank; provide an input based on the measurements to a trained model that is configured to generate…
CONTROLLING LIGHT SOURCE WAVELENGTHS FOR SELECTABLE PHASE SHIFTS BETWEEN PIXELS IN DIGITAL LITHOGRAPHY SYSTEMS
Granted: December 21, 2023
Application Number:
20230408807
A digital lithography system may adjust a wavelength of the light source to compensate for tilt errors in micromirrors while maintaining a perpendicular direction for the reflected light. Adjacent pixels may have a phase shift that is determined by an optical path difference between their respective light beams. This phase shift may be preselected to be any value by generating a corresponding wavelength at the light source based on the optical path difference. To generate a specific…
PUMP LINER FOR PROCESS CHAMBER
Granted: December 21, 2023
Application Number:
20230407473
Embodiments of the present disclosure are related to directed to a pump liner for a process chamber. The pump liner is aligned with particular components in the process chamber so that there is an upper gap and a lower gap between the pump liner and the particular processing chamber components (e.g., an edge ring). The pump liner advantageously reduces side to side variation in temperature and gas flow based on its alignment with particular components in the process chamber (e.g., the…
DEFECT FREE GERMANIUM OXIDE GAP FILL
Granted: December 21, 2023
Application Number:
20230407468
Methods for forming defect-free gap fill materials comprising germanium oxide are disclosed. In some embodiments, the gap fill material is deposited by exposing a substrate surface to a germane precursor and an oxidant simultaneously. The germane precursor may be flowed intermittently. The substrate may also be exposed to a second oxidant to increase the relative concentration of oxygen within the gap fill material. A process for removal of germanium oxide is also disclosed.
METHOD OF FORMING CARBON-BASED SPACER FOR EUV PHOTORESIST PATTERNS
Granted: December 14, 2023
Application Number:
20230402285
Methods of depositing a conformal carbon-containing spacer layer are described. Exemplary processing methods may include flowing a first precursor over a patterned surface and a substrate to form a first portion of an initial carbon-containing film on the structure. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial carbon-containing film. The methods may…
PATTERNING LAYER MODIFICATION USING DIRECTIONAL RADICAL RIBBON BEAM
Granted: December 14, 2023
Application Number:
20230402284
Disclosed are approaches for forming semiconductor patterning features. One method may include providing a plurality of openings through a patterning layer of a semiconductor device, wherein each opening of the plurality of openings is defined by a sidewall of the patterning layer, and wherein the patterning layer is a resist layer or a carbon-based layer. The method may further include removing a portion of the patterning layer by directing a beam of neutral reactive radicals into the…
UNIFORM IN SITU CLEANING AND DEPOSITION
Granted: December 14, 2023
Application Number:
20230402261
Exemplary semiconductor processing systems may include an output manifold that defines at least one plasma outlet. The systems may include a gasbox disposed beneath the output manifold. The gasbox may include an inlet side facing the output manifold and an outlet side opposite the inlet side. The gasbox may include an inner wall that defines a central fluid lumen. The inner wall may taper outward from the inlet side to the outlet side. The systems may include an annular spacer disposed…
MEMORY CELL SELECTOR FOR HIGH-VOLTAGE SET AND RESET OPERATIONS
Granted: December 14, 2023
Application Number:
20230402093
A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a terminal of the memory element during a reset operation. Similarly, a second transistor may open a conductive path between a low voltage and the terminal of the memory element during a set operation. Some implementations may add a third transistor in series with…
THROTTLE VALVE AND FORELINE CLEANING USING A MICROWAVE SOURCE
Granted: December 7, 2023
Application Number:
20230390811
Exemplary semiconductor processing systems may include a processing chamber defining a processing region. The systems may include a foreline coupled with the processing chamber, the foreline defining a fluid conduit. The systems may include a radical generator having an inlet and an outlet. The outlet may be fluidly coupled with the foreline. The systems may include a gas source fluidly coupled with the inlet of the radical generator. The systems may include a throttle valve coupled with…
RUTHENIUM CARBIDE FOR DRAM CAPACITOR MOLD PATTERNING
Granted: December 7, 2023
Application Number:
20230395391
Methods of forming electronic devices and film stacks comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and patterned photoresist are formed, and the pattern of the patterned photoresist are transferred into the ruthenium carbide hard mask. Film stacks comprising the ruthenium carbide hard mask on the capacitor mold are also described.
RNA retrieval process for preparing formalin-fixed, paraffin-embedded (FFPE) tissue samples for in situ hybridization
Granted: December 7, 2023
Application Number:
20230392196
This disclosure provides a technology for optimally retrieving and presenting RNA in tissue samples for analysis by in situ hybridization, simultaneously preserving morphological and antigenic features of the tissues. Formalin-fixed, paraffin-embedded (FFPE) sections of a tissue sample are dried on glass slides, and deparaffinized by incubating in successive mixtures of organic solvents. The slides are then placed in a pressure chamber, where they are uniformly heated to about 120° C.…
FACE-UP WAFER ELECTROCHEMICAL PLANARIZATION APPARATUS
Granted: December 7, 2023
Application Number:
20230390887
Exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. The apparatuses may include a retaining wall extending from the chuck body. The apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. The apparatuses may include a spindle that is positionable over the chuck body. The apparatuses may include an end effector coupled with a lower end of the spindle. The end effector may…
