BACKFLUSH SEAL CLEANING APPARATUS
Granted: March 20, 2025
Application Number:
20250091094
Exemplary seal cleaning apparatuses may include at least one support that is configured to receive a seal. The apparatuses may include a tool arm that is positionable within an interior of the seal. The apparatuses may include a pad holder that is rotatably coupled with the tool arm. The pad holder may include a body having a first end and a second end. The first end may define a channel that is configured to receive a cleaning pad. The body may define an aperture that extends from the…
ULTRA-THIN BODY ARRAY TRANSISTOR FOR 4F2
Granted: March 20, 2025
Application Number:
20250098149
The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality…
METAL-CONTAINING HARDMASK OPENING METHODS USING BORON-AND-HALOGEN-CONTAINING PRECURSORS
Granted: March 20, 2025
Application Number:
20250095990
Exemplary semiconductor processing methods may include providing a boron-and-halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of metal-containing hardmask material may be disposed on the substrate. A layer of silicon-containing material may be disposed on the layer of metal-containing hardmask material. The methods may include forming plasma effluents…
IN-SITU SIDEWALL PASSIVATION TOWARD THE BOTTOM OF HIGH ASPECT RATIO FEATURES
Granted: March 20, 2025
Application Number:
20250095984
Methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A feature may extend through one or more layers of material disposed on the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The methods may include contacting the…
SEMICONDUCTOR CHAMBER COMPONENTS WITH ADVANCED DUAL LAYER NICKEL-CONTAINING COATINGS
Granted: March 20, 2025
Application Number:
20250095968
Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to…
CONOSCOPIC WAFER ORIENTATION FOR ION IMPLANTATION
Granted: March 20, 2025
Application Number:
20250095958
An ion implanter may include an ion source to generate an ion beam. The ion implanter may include a set of beamline components to direct the ion beam to a substrate along a beam axis, as well as a process chamber to house the substrate to receive the ion beam. The ion implanter may include a conoscopy system, comprising: an illumination source to direct light to a substrate position; a first polarizer, having a first polarization axis, disposed between the illumination source and the…
METHOD AND SYSTEM FOR CALIBRATION OF DIFFRACTION ANGLES
Granted: March 20, 2025
Application Number:
20250095955
Disclosed are method and system for calibrating a tilt angle of an electron beam of a backscattered scanning electron microscope including scanning a bare wafer at a plurality of electron beam tilt and azimuth angles, thereby obtaining a calibration map representing a crystal orientation of the bare wafer, selecting a tilt angle and defining an expected diffraction pattern associated with the tilt angle, based on the calibration map; scanning a patterned wafer at the selected tilt angle,…
CONOSCOPIC WAFER ORIENTATION APPARATUS AND ION IMPLANTER INCLUDING SAME
Granted: March 20, 2025
Application Number:
20250095952
An ion implanter, including an ion source generating an ion beam, a set of beamline components directing the ion beam to a substrate along a beam axis, normal to a reference plane, a process chamber housing the substrate to receive the ion beam, and a conoscopy system. The conoscopy system may include: an illumination source directing light to a substrate position, a first polarizer assembly, comprising a first polarizer element and first pair of lenses, disposed on opposite sides of the…
HIGH CONDUCTANCE VARIABLE ORIFICE VALVE
Granted: March 20, 2025
Application Number:
20250092953
Variable orifice valves comprising a first fixed plate, a second fixed plate and a movable plate between are described. The movable plate is connected to the first fixed plate and the second fixed plate by sealing elements. The movable plate is moved closer to or further from the first fixed plate by rotation of an actuator ring that rotates at least two rotary elements connected to the movable plate. A needle on the movable plate engages an opening in the valve to seal or open the valve…
ELECTROCHEMICAL DEPOSITION SYSTEMS WITH ENHANCED CRYSTALLIZATION PREVENTION FEATURES
Granted: March 20, 2025
Application Number:
20250092559
Electrochemical deposition systems and methods are described that have enhanced crystallization prevention features. The systems may include a bath vessel operable to hold an electrochemical deposition fluid having a metal salt dissolved in water. The systems may also include sensors including a thermometer and concentration sensor operable to measure characteristics of the electrochemical deposition fluid. The systems further include a computer configured to perform operations that…
MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR COMPLEMENTARY FIELD-EFFECT TRANSISTORS
Granted: March 13, 2025
Application Number:
20250089355
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first…
MATERIALS AND METHODS FOR COMPLEMENTARY FIELD-EFFECT TRANSISTORS HAVING MIDDLE DIELECTRIC ISOLATION LAYER
Granted: March 13, 2025
Application Number:
20250089345
Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure…
METHOD AND MATERIAL SYSTEM FOR TUNABLE HYBRID BOND INTERCONNECT RESISTANCE
Granted: March 13, 2025
Application Number:
20250087573
The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with…
SYSTEMS AND METHODS FOR SELECTIVE METAL-CONTAINING HARDMASK REMOVAL
Granted: March 13, 2025
Application Number:
20250087494
Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include…
METHODS OF FORMING SILICON NITRIDE FILMS
Granted: March 13, 2025
Application Number:
20250087477
Methods of depositing improved quality silicon nitride (SixNy) films are disclosed. Exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (He) and nitrogen (N2), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second…
MULTI-STAGE PUMPING LINER
Granted: March 13, 2025
Application Number:
20250087471
Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in…
SUPPORT UNIT
Granted: March 13, 2025
Application Number:
20250084954
A support unit for supporting a supported element, including (a) a spherical joint, (b) a pressure applying unit that is configured to maintain contact between a spherical outer surface and a base, (c) a position control unit that is configured to contact the spherical joint positioning element at multiple contact points and to set values of a first angle of rotation and a second angle of rotation of the spherical outer surface. The spherical joint is located above the position control…
ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL
Granted: March 6, 2025
Application Number:
20250076753
Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate.…
METHODS AND STRUCTURES FOR HIGH STRENGTH DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079312
A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric…
SUBSTRATE PRE-ALIGNER
Granted: March 6, 2025
Application Number:
20250079221
A substrate alignment system that includes (i) an illumination unit that is configured to illuminate an illuminated region that comprises an entire edge of a substrate; (ii) a sensing unit having a field of view that covers the entire edge of the substrate even when the substrate is misaligned, the sensing unit includes a sensor that is preceded by a fish eye lens, the sensor is configured to generate detection signals of the entire edge of the substrate; and (iii) a processing circuit…
