MODEL-BASED ACOUSTO-OPTIC DEPTH-METROLOGY OF SPECIMENS
Granted: April 10, 2025
Application Number:
20250116597
Disclosed herein is a method for non-destructive depth-profiling including projecting a pulsed pump beam into a specimen, projecting a pulsed probe beam thereinto, and sensing light returned therefrom to obtain a measured signal. Each probe pulse is configured to undergo Brillouin scattering off a primary acoustic pulse induced by the directly preceding pump pulse, so as to be scattered there off at a respective depth within the specimen. The method further includes executing an…
SELF-ALIGNED BIT LINE FOR 4F2 DRAM
Granted: April 10, 2025
Application Number:
20250120069
The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first…
PEDESTAL HEATER WITH SUBSTRATE TEMPERATURE MEASUREMENT SYSTEM
Granted: April 10, 2025
Application Number:
20250118578
Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end…
CERAMIC RF RETURN KIT DESIGN
Granted: April 10, 2025
Application Number:
20250118577
Exemplary semiconductor processing systems may include a chamber body having a bottom plate. The systems may include a substrate support disposed within the chamber body. The substrate support may include a support plate and a shaft. The shaft may include a cooling hub that extends through the bottom plate. The shaft may include a ground shaft that is seated atop the cooling hub. The ground shaft may include a ceramic material. The systems may include an inner isolator coupled with a…
ANNEAL CHAMBER
Granted: April 10, 2025
Application Number:
20250118572
Exemplary anneal chambers may include a base that defines a chamber interior. The base may include a cooling plate within the chamber interior. The base and the cooling plate may be integral with one another. The chambers may include a lid that is coupled with the base. The chambers may include a heater plate mounted in the chamber interior alongside the cooling plate. The chambers may include a transfer hoop movably coupled within the chamber interior. The base may define a first…
BOW MITIGATION IN HIGH ASPECT RATIO OXIDE AND NITRIDE ETCHES
Granted: April 10, 2025
Application Number:
20250118570
Methods of semiconductor processing may include forming plasma effluents. The plasma effluents may then contact a carbon-containing hardmask and an oxide cap. The plasma effluents can etch one or more features in the oxide cap through one or more apertures of the carbon-containing hardmask. Etching can create a tapered profile for one or more features in the oxide cap. The one or more features can be characterized by a critical dimension at the bottom of the one or more features. The…
TITANIUM NITRIDE GAPFILL PROCESSES FOR SEMICONDUCTOR STRUCTURES
Granted: April 10, 2025
Application Number:
20250118563
One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing a gapfill material, such as titanium nitride (TiN), in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure…
SELECTIVE HARDMASK ETCH FOR SEMICONDUCTOR PROCESSING
Granted: April 10, 2025
Application Number:
20250118557
Methods of semiconductor processing may include forming plasma effluents of a hydrogen-and-fluorine-containing precursor. The plasma effluents may then contact a silicon-containing hardmask material and a photoresist material. The silicon-containing hardmask material can overlay an organic material overlaying a substrate in a processing region of a semiconductor processing chamber. Etching the silicon-containing hardmask material with the plasma effluents while the photoresist material…
METHOD TO IMPROVE WAFER EDGE UNIFORMITY
Granted: April 10, 2025
Application Number:
20250118539
Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of…
MICROWAVE HIGH-DENSITY PLASMA FOR SELECTIVE ETCH
Granted: April 10, 2025
Application Number:
20250118536
Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion…
ELECTROPLATING CHAMBER USING JET ARRAY TO ENABLE HIGH MASS-TRANSFER
Granted: April 10, 2025
Application Number:
20250116028
Exemplary electroplating systems may include a vessel. The systems may include a head that is configured to hold a substrate. The head may be positionable within an interior of the vessel. The systems may include a spray jet array disposed within the interior of the vessel. The spray jet array may include a plate defining a plurality of apertures through a thickness of the plate. The systems may include at least one fluid pump that is fluidly coupled with an inlet end of each of the…
ARC REDUCTION AND RF CONTROL FOR ELECTROSTATIC CHUCKS IN SEMICONDUCTOR PROCESSING
Granted: April 10, 2025
Application Number:
20250116001
A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or…
CURABLE FORMULATIONS FOR POLISHING PADS
Granted: April 10, 2025
Application Number:
20250115698
Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the…
CURABLE FORMULATIONS FOR POLISHING PADS
Granted: April 10, 2025
Application Number:
20250115697
Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the…
SMART FACEPLATE/SHOWERHEAD USING SHAPE MEMORY ALLOY
Granted: April 10, 2025
Application Number:
20250114806
Exemplary substrate processing system faceplates may include a plate that is characterized by a first surface and a second surface opposite the first surface. The second surface may define a plurality of recesses that extend through a portion of a thickness of the plate. The plate may define a plurality of apertures through the thickness of the plate. Each aperture may extend through a bottom surface of one recess of the plurality of recesses. Each recess may have a greater diameter than…
CHEMICAL MECHANICAL POLISHING EDGE CONTROL WITH PAD RECESSES
Granted: April 3, 2025
Application Number:
20250108477
A Chemical Mechanical Polishing (CMP) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. This may cause uneven material removal as the substrate moves along the surface of the polishing pad. Therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. The one or more recesses may be connected to channels that extend radially outward from…
LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
Granted: April 3, 2025
Application Number:
20250112056
Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing…
BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS
Granted: April 3, 2025
Application Number:
20250112046
Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The…
LOW ENERGY TREATMENT TO PASSIVATE SiC SUBSTRATE DEFECTS
Granted: April 3, 2025
Application Number:
20250112043
Disclosed herein are methods for passivating SiC substrate defects using a low-energy treatment. In some embodiments, a method may include providing a silicon carbide (SIC) substrate, treating the SiC substrate using an ion implant or a plasma doping process, forming a first epitaxial layer over an upper surface of the SiC substrate after the SiC substrate is treated, and forming a second epitaxial layer over the first epitaxial layer.
INVERTING IMPLANTER PROCESS MODEL FOR PARAMETER GENERATION
Granted: April 3, 2025
Application Number:
20250112026
Techniques for inverting implanter process model for parameter generation are described. A method comprises receiving a set of process parameters and associated values for an ion implanter by an inverted control model, the inverted control model comprising an artificial neural network (ANN), predicting a set of control parameters and associated values for the ion implanter based on the set of process parameters and associated values by the inverted control model, and presenting the set…
