REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE AND METHOD OF FABRICATION THEREFOR
Granted: October 17, 2024
Application Number:
20240347602
A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be…
COATING COMPONENTS FOR SEMICONDUCTOR PROCESSING WITH FLUORINE-CONTAINING MATERIALS
Granted: October 17, 2024
Application Number:
20240347336
Exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The one or more deposition precursors may include a metal-containing precursor and a fluorine-containing precursor. The methods may include depositing a layer of material on the component for semiconductor processing in the processing region. The layer of…
PROCESS CHAMBER VACUUM SEAL LEAKAGE REDUCTION
Granted: October 17, 2024
Application Number:
20240344608
Sealing bodies comprising a first body having a top surface and a bottom surface defining a thickness thereof. An inlet conduit and an outlet conduit are in fluid communication with one or more of the top surface, the bottom surface, or a top channel formed in the top surface or a bottom channel formed in the bottom surface.
Molybdenum (0) Precursors For Deposition Of Molybdenum Films
Granted: October 17, 2024
Application Number:
20240343748
Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.
APPARATUS, SYSTEM AND TECHNIQUES FOR MASS ANALYZED ION BEAM
Granted: October 10, 2024
Application Number:
20240339287
An apparatus may include an electrodynamic mass analysis (EDMA) assembly disposed downstream from the convergent ion beam assembly. The EDMA assembly may include a first stage, comprising a first upper electrode, disposed above a beam axis, and a first lower electrode, disposed below the beam axis, opposite the first upper electrode. The EDMA assembly may also include a second stage, disposed downstream of the first stage and comprising a second upper electrode, disposed above the beam…
4F2 VERTICAL ACCESS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT
Granted: October 10, 2024
Application Number:
20240341082
The present technology includes vertical cell dynamic random-access memory (DRAM) array access transistors with improved hole distribution. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect…
METHOD OF FORMING A METAL LINER FOR INTERCONNECT STRUCTURES
Granted: October 10, 2024
Application Number:
20240339358
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R?, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to…
AUTOMATIC CONTROL OF SUBSTRATES
Granted: October 10, 2024
Application Number:
20240339341
The present technology includes methods and systems for improving substrate processing. Methods and systems include disposing a substrate on a pedestal that includes a plurality of heating zones each with an independent heater, processing the substrate according to an initial substrate processing recipe that includes an initial pedestal temperature, collecting initial substrate feedback of one or more substrate properties and providing the data as a first input to a substrate control…
FLOW FOR HIGH RESOLUTION STEREOSCOPIC MEASUREMENTS
Granted: October 10, 2024
Application Number:
20240339289
A method of determining a depth of a hole milled into a first region of a sample, comprising: positioning the sample in a processing chamber having a charged particle beam column; milling a hole in the first region of the sample using a charged particle beam generated by the charged particle beam column; identifying a first registration mark at an upper level of the milled hole; identifying a second registration mark at a lower level of the milled hole; taking a first set of images at a…
HYBRID APPARATUS, SYSTEM AND TECHNIQUES FOR MASS ANALYZED ION BEAM
Granted: October 10, 2024
Application Number:
20240339288
An apparatus, including an electrodynamic mass analysis (EDMA) assembly. The EDMA assembly may include a first upper electrode, disposed above a beam axis; and a first lower electrode, disposed below the beam axis, opposite the first upper electrode, the EDMA assembly arranged to receive a first RF voltage signal at a first frequency. The apparatus may include a deflection assembly, disposed downstream to the EDMA assembly, the deflection assembly comprising a blocker, disposed along the…
HIGH TEMPERATURE METAL SEALS FOR VACUUM SEGREGATION
Granted: October 10, 2024
Application Number:
20240337318
Embodiments of the present disclosure are related to directed to a pressure seal for a process chamber. The pressure seal comprises a bottom portion, a compressible middle portion on the bottom portion, and a top portion on the compressible middle portion. The disclosed pressure seal is configured to reduce pumping time of a process region in an interior volume of a processing chamber compared to a process chamber that does not include a pressure seal. Processing chambers including the…
PLATING SEAL WITH IMPROVED SURFACE
Granted: October 10, 2024
Application Number:
20240337040
The present technology includes monolithic electroplating seals, such as electroplating seals formed utilizing additive manufacturing. Seals include an external seal member and an internal seal member. The external seal member includes an inner annular radius, an outer annular radius, and an external seal member body defined between an exterior surface and an interior surface opposite the exterior surface. The exterior surface is formed from at least one polymer layer having a porosity…
CERAMIC SYNTHESIS THROUGH SURFACE COATING OF POWDERS
Granted: October 3, 2024
Application Number:
20240327300
Exemplary processing methods may include providing a powder to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The methods may include generating plasma effluents of the one or more deposition precursors. The methods may include depositing a layer of material on the powder in the processing region. The layer of material may include a corrosion-resistant material. A temperature within the processing…
MEMORY DEVICES AND METHODS OF FORMING THE SAME
Granted: October 3, 2024
Application Number:
20240334683
Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer…
GRADIENT METAL LINER FOR INTERCONNECT STRUCTURES
Granted: October 3, 2024
Application Number:
20240332075
Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the…
PROTECTIVE CAPPING LAYER FOR AREA SELECTIVE DEPOSITION
Granted: October 3, 2024
Application Number:
20240332072
Described are methods of forming a protective capping layer on a metal layer of a semiconductor substrate. A metal layer is deposited using a metal precursor and a reactant pulsed to form the metal layer having a reactive surface. The number of cycles can be in a range of from 1 to 10 cycles or from 2 to 5 cycles or from 2 to 100 cycles. The metal layer is then exposed to a long chain precursor (e.g., primary amines, alcohols, thiols, phosphines, selenols) and a metal precursor to form a…
METHODS TO IMPROVE QUALITY SILICON-CONTAINING MATERIALS
Granted: October 3, 2024
Application Number:
20240332006
Exemplary methods of forming a silicon-and-carbon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor to the processing region. The methods may include generating plasma effluents of the silicon-containing precursor and plasma effluents of the…
METHODS FOR DEPOSITING DIELECTRIC FILMS WITH INCREASED STABILITY
Granted: October 3, 2024
Application Number:
20240332005
Embodiments include semiconductor processing methods to form dielectric films on semiconductor substrates are described. The methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include providing an inert precursor to the processing region of the semiconductor processing chamber. The methods may include…
THERMAL PROCESSING CHAMBER STATE BASED ON THERMAL SENSOR READINGS
Granted: October 3, 2024
Application Number:
20240327988
A method of characterizing thermal processing chambers may include training a model using temperature rate-of-change data from existing thermal processing chambers. A supervised learning process may label the rate-of-change data based on deposition profiles on substrates. The trained model may be used to characterize another chamber to determine if the predicted performance will match the chambers used to train the model. An inert process using carrier gasses may be used to capture…
PROCESSING SYSTEMS FOR METAL PRECURSOR SYNTHESIS AND DEPOSITION
Granted: October 3, 2024
Application Number:
20240327983
Processing chambers for forming metal-containing precursors and deposition of pure metal films are disclosed. Also disclosed are deposition methods that include forming a metal-containing precursor and depositing the metal-containing precursor on a substrate to form a metal film in a single processing chamber.
