METHODS OF IMPROVING PMOS TRANSISTOR PERFORMANCE
Granted: March 6, 2025
Application Number:
20250081593
Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure…
CONTACT RESISTANCE REDUCTION FOR DIRECT BACKSIDE CONTACT
Granted: March 6, 2025
Application Number:
20250081592
Disclosed herein are methods for direct backside contact formation. In some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. The method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is…
MOSFET Gate Shielding Using an Angled Implant
Granted: March 6, 2025
Application Number:
20250081583
Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the…
GATE ALL AROUND 4F2 DRAM
Granted: March 6, 2025
Application Number:
20250081432
Vertical cell dynamic random-access memory (DRAM) arrays and methods of forming arrays with improved stability and word line resistivity are provided. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality…
METHODS AND STRUCTURES FOR HIGH STRENGTH ASYMMETRIC DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079357
A first structure for semiconductor devices having a dielectric film on the top surface can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The top surface of the dielectric film of the first structure can be hybrid bonded to a dielectric layer of a second structure. The dielectric film of the first structure and the dielectric layer of the second structure can be different…
METHOD AND MATERIAL SYSTEM FOR HIGH STRENGTH SELECTIVE DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079356
A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure…
METHODS AND STRUCTURES FOR HIGH STRENGTH DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079312
A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric…
ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL
Granted: March 6, 2025
Application Number:
20250076753
Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate.…
GAS AMPLIFIER FOR CMP COOLING
Granted: March 6, 2025
Application Number:
20250073850
A chemical mechanical polishing chamber may include a platen disposed within the chemical mechanical polishing chamber, the platen configured to support a polishing pad. The chamber may also include a slurry delivery arm configured to deliver a slurry to the polishing pad during a chemical mechanical polishing process. The chamber may include an arm may include one or more brackets, mechanically attached to an internal side of the chemical mechanical polishing chamber and positioned over…
ADAPTIVE WAFER BOW MANAGEMENT
Granted: February 27, 2025
Application Number:
20250069959
A sensor can be configured to measure wafer bowing characteristics associated with a bow of a wafer after a first fabrication process is performed on the wafer in a first processing chamber and before a second fabrication process is performed on the wafer in a second processing chamber. A transfer chamber, including the sensor, can be coupled to a first process chamber and a second process chamber. The wafer bowing characteristics can be used by a controller to determine recipe…
METHODS OF ETCHING SILICON-AND-OXYGEN-CONTAINING FEATURES AT LOW TEMPERATURES
Granted: February 27, 2025
Application Number:
20250069895
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of a silicon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include contacting the…
METHODS OF SELECTIVELY ETCHING SILICON NITRIDE
Granted: February 27, 2025
Application Number:
20250069894
Embodiments of the present disclosure are directed to selective etching processes. The processes include flowing a precursor comprising one or more of an interhalogen, a halogen-containing species, a pseudohalogen species, a mixture of one or more of the interhalogen, the halogen-containing species, or the pseudohalogen species and an amine or a phosphine, or a mixture of one or more of the interhalogen, the halogen-containing species, or the pseudohalogen species with a…
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND HIGH MECHANICAL STRENGTH
Granted: February 27, 2025
Application Number:
20250069884
Exemplary semiconductor processing methods may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursors may include Si—O bonding. The methods may include forming a plasma of the first silicon-containing precursor and the second silicon-containing…
MULTILAYER COATING FOR CORROSION RESISTANCE
Granted: February 27, 2025
Application Number:
20250069857
Exemplary methods of coating a metal-containing component are described. The methods are developed to increase corrosion resistance and improve coating adhesion to a metal substrate. The methods include forming a bonding layer on a metal substrate, where the bonding layer includes an oxide of a metal in the metal substrate. The coating methods further include depositing a stress buffer layer on the bonding layer, where the stress buffer layer is characterized by a stress buffer layer…
SEAM PERFORMANCE IMPROVEMENT USING HYDROXYLATION FOR GAPFILL
Granted: February 27, 2025
Application Number:
20250066913
Methods of filling a feature on a semiconductor substrate may include performing a process to fill the feature on the semiconductor substrate by repeatedly performing first operations. First operations can include providing a silicon-containing precursor. First operations can include contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate. First operations can include purging the semiconductor…
ROBOT BLADE AND WAFER BREAKAGE PREVENTION SYSTEM
Granted: February 27, 2025
Application Number:
20250065509
An apparatus that includes an end effector for handling and transporting wafers, the end effector including: a base portion having a first end adapted to be attached to a robot; a wafer support platform having a surface to support a wafer, a slidable joint coupling the base portion to the wafer support platform; and a sensor configured to detect when the wafer support platform slides relative to the base portion beyond a predetermined distance.
PLASMA ETCHING IN SEMICONDUCTOR PROCESSING
Granted: February 20, 2025
Application Number:
20250062131
Methods of semiconductor processing may include forming plasma effluents of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-and-fluorine-containing precursor like silicon tetrafluoride). The plasma effluents may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. The mask material may have one or more apertures therein that allow the plasma…
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND INCREASED DENSITY
Granted: February 20, 2025
Application Number:
20250062117
Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-oxygen-and-carbon-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-oxygen—and—carbon-containing material on the substrate. The…
METHODS OF ETCHING OXYGEN-CONTAINING FEATURES AT LOW TEMPERATURES
Granted: February 13, 2025
Application Number:
20250054770
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of oxygen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The methods may include contacting the substrate…
METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERS
Granted: February 13, 2025
Application Number:
20250056871
Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.
