SEMICONDUCTOR AIRGAP SPACER AND FABRICATION METHODS
Granted: April 3, 2025
Application Number:
20250113577
Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective…
LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
Granted: April 3, 2025
Application Number:
20250112056
Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing…
CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THICKNESS LOSS
Granted: April 3, 2025
Application Number:
20250112054
Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant…
DIRECTIONAL RIE FEATURE RECTANGULARITY
Granted: April 3, 2025
Application Number:
20250112052
Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may…
BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS
Granted: April 3, 2025
Application Number:
20250112046
Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The…
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND ENHANCED ELECTRICAL PROPERTIES
Granted: April 3, 2025
Application Number:
20250112038
Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-nitrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-carbon-and-nitrogen-containing material on the substrate. The…
INVERTING IMPLANTER PROCESS MODEL FOR PARAMETER GENERATION
Granted: April 3, 2025
Application Number:
20250112026
Techniques for inverting implanter process model for parameter generation are described. A method comprises receiving a set of process parameters and associated values for an ion implanter by an inverted control model, the inverted control model comprising an artificial neural network (ANN), predicting a set of control parameters and associated values for the ion implanter based on the set of process parameters and associated values by the inverted control model, and presenting the set…
CHEMICAL MECHANICAL POLISHING EDGE CONTROL WITH PAD RECESSES
Granted: April 3, 2025
Application Number:
20250108477
A Chemical Mechanical Polishing (CMP) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. This may cause uneven material removal as the substrate moves along the surface of the polishing pad. Therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. The one or more recesses may be connected to channels that extend radially outward from…
LOW RESISTIVITY METAL STACKS AND METHODS OF DEPOSITING THE SAME
Granted: March 27, 2025
Application Number:
20250105013
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. The tungsten (W) layer has a thickness in a range of from 5 ? to 30 ? and the molybdenum (Mo) layer has a thickness in a range of from 80 ? to 200 ?. In some embodiments, the metal stack has a resistivity of less than or equal to 10…
DUAL WORK FUNCTION WORD LINE FOR 4F2
Granted: March 27, 2025
Application Number:
20250107068
The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality…
RECOMBINATION CHANNELS FOR ANGLE CONTROL OF NEUTRAL REACTIVE SPECIES
Granted: March 27, 2025
Application Number:
20250104976
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a…
MODIFIED STACKS FOR 3D NAND
Granted: March 27, 2025
Application Number:
20250101578
Exemplary semiconductor structures may include a stack of layers overlying a substrate. The stack of layers may include a first portion of layers, a second portion of layers overlying the first portion of layers, and a third portion of layers overlying the second portion of layers. The first portion of layers, the second portion of layers, and the third portion of layers may include alternating layers of a silicon oxide material and a silicon nitride material. One or more apertures may…
BACKFLUSH SEAL CLEANING APPARATUS
Granted: March 20, 2025
Application Number:
20250091094
Exemplary seal cleaning apparatuses may include at least one support that is configured to receive a seal. The apparatuses may include a tool arm that is positionable within an interior of the seal. The apparatuses may include a pad holder that is rotatably coupled with the tool arm. The pad holder may include a body having a first end and a second end. The first end may define a channel that is configured to receive a cleaning pad. The body may define an aperture that extends from the…
ULTRA-THIN BODY ARRAY TRANSISTOR FOR 4F2
Granted: March 20, 2025
Application Number:
20250098149
The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality…
METAL-CONTAINING HARDMASK OPENING METHODS USING BORON-AND-HALOGEN-CONTAINING PRECURSORS
Granted: March 20, 2025
Application Number:
20250095990
Exemplary semiconductor processing methods may include providing a boron-and-halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of metal-containing hardmask material may be disposed on the substrate. A layer of silicon-containing material may be disposed on the layer of metal-containing hardmask material. The methods may include forming plasma effluents…
SEMICONDUCTOR CHAMBER COMPONENTS WITH ADVANCED DUAL LAYER NICKEL-CONTAINING COATINGS
Granted: March 20, 2025
Application Number:
20250095968
Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to…
CONOSCOPIC WAFER ORIENTATION FOR ION IMPLANTATION
Granted: March 20, 2025
Application Number:
20250095958
An ion implanter may include an ion source to generate an ion beam. The ion implanter may include a set of beamline components to direct the ion beam to a substrate along a beam axis, as well as a process chamber to house the substrate to receive the ion beam. The ion implanter may include a conoscopy system, comprising: an illumination source to direct light to a substrate position; a first polarizer, having a first polarization axis, disposed between the illumination source and the…
METHOD AND SYSTEM FOR CALIBRATION OF DIFFRACTION ANGLES
Granted: March 20, 2025
Application Number:
20250095955
Disclosed are method and system for calibrating a tilt angle of an electron beam of a backscattered scanning electron microscope including scanning a bare wafer at a plurality of electron beam tilt and azimuth angles, thereby obtaining a calibration map representing a crystal orientation of the bare wafer, selecting a tilt angle and defining an expected diffraction pattern associated with the tilt angle, based on the calibration map; scanning a patterned wafer at the selected tilt angle,…
CONOSCOPIC WAFER ORIENTATION APPARATUS AND ION IMPLANTER INCLUDING SAME
Granted: March 20, 2025
Application Number:
20250095952
An ion implanter, including an ion source generating an ion beam, a set of beamline components directing the ion beam to a substrate along a beam axis, normal to a reference plane, a process chamber housing the substrate to receive the ion beam, and a conoscopy system. The conoscopy system may include: an illumination source directing light to a substrate position, a first polarizer assembly, comprising a first polarizer element and first pair of lenses, disposed on opposite sides of the…
HIGH CONDUCTANCE VARIABLE ORIFICE VALVE
Granted: March 20, 2025
Application Number:
20250092953
Variable orifice valves comprising a first fixed plate, a second fixed plate and a movable plate between are described. The movable plate is connected to the first fixed plate and the second fixed plate by sealing elements. The movable plate is moved closer to or further from the first fixed plate by rotation of an actuator ring that rotates at least two rotary elements connected to the movable plate. A needle on the movable plate engages an opening in the valve to seal or open the valve…
