ATOMIC LAYER DEPOSITION OF SILICON-CARBON-AND-NITROGEN-CONTAINING MATERIALS
Granted: October 3, 2024
Application Number:
20240332001
Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The substrate may define a feature. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a silicon-carbon-and-nitrogen-containing material on the substrate. The methods may include providing a second…
METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE
Granted: October 3, 2024
Application Number:
20240332388
One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.
GRADIENT METAL LINER FOR INTERCONNECT STRUCTURES
Granted: October 3, 2024
Application Number:
20240332075
Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the…
METHOD FOR ETCHING HIGH ASPECT RATIO STRUCTURES
Granted: October 3, 2024
Application Number:
20240332031
A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation…
COMPRESSIVE FILMS FOR LARGE AREA GAPFILL
Granted: October 3, 2024
Application Number:
20240332028
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. The methods may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of greater than or about ?200 MPa. The methods may include annealing the substrate at a temperature of greater…
SILICON-AND-GERMANIUM ETCHING
Granted: October 3, 2024
Application Number:
20240332027
Exemplary methods of semiconductor processing may include providing a first fluorine-containing precursor to a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the first fluorine-containing precursor in the remote plasma system. The methods may include providing plasma effluents of the first fluorine-containing precursor to a processing region of the semiconductor processing chamber. The methods may include providing a…
ION IMPLANTATION FOR REDUCED ROUGHNESS OF SILICON NITRIDE
Granted: October 3, 2024
Application Number:
20240332009
Exemplary methods of semiconductor processing may include forming a layer of silicon nitride on a semiconductor substrate. The layer of silicon nitride may be characterized by a first roughness. The methods may include performing a post-deposition treatment on the layer of silicon nitride. The methods may include reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride may be characterized by a second roughness less than the first roughness.
INTEGRATED DIPOLE REGION FOR TRANSISTOR
Granted: October 3, 2024
Application Number:
20240332008
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of…
METHODS TO IMPROVE QUALITY SILICON-CONTAINING MATERIALS
Granted: October 3, 2024
Application Number:
20240332006
Exemplary methods of forming a silicon-and-carbon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor to the processing region. The methods may include generating plasma effluents of the silicon-containing precursor and plasma effluents of the…
METHODS FOR DEPOSITING DIELECTRIC FILMS WITH INCREASED STABILITY
Granted: October 3, 2024
Application Number:
20240332005
Embodiments include semiconductor processing methods to form dielectric films on semiconductor substrates are described. The methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include providing an inert precursor to the processing region of the semiconductor processing chamber. The methods may include…
SYSTEMS AND METHODS FOR NANOHOLE WET CLEANS
Granted: October 3, 2024
Application Number:
20240331999
Exemplary semiconductor processing methods may include providing a substrate to a processing region of a semiconductor processing chamber. The substrate may include an alternating stack of materials. A feature may extend through the alternating stack of materials. One material of the alternating stack of materials may include a silicon-containing material. A native oxide material may be disposed on at least a portion of exposed surfaces of the silicon-containing material. The methods may…
CERAMIC SYNTHESIS THROUGH SURFACE COATING OF POWDERS
Granted: October 3, 2024
Application Number:
20240327300
Exemplary processing methods may include providing a powder to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The methods may include generating plasma effluents of the one or more deposition precursors. The methods may include depositing a layer of material on the powder in the processing region. The layer of material may include a corrosion-resistant material. A temperature within the processing…
PRECLEAN AND ENCAPSULATION OF MICROLED FEATURES
Granted: September 26, 2024
Application Number:
20240322073
Method for cleaning and encapsulating microLED features are disclosed. Some embodiments provide for a wet clean process and a dry clean process to remove contaminants from the microLED feature. Some embodiments provide for the encapsulation of a clean microLED feature. Some embodiments provide improved crystallinity of the microLED feature and the capping layer. Some embodiments provide improved EQE of microLED devices formed from the disclosed microLED features.
METHOD TO IMPROVE INTERCONNECT COEFFICIENT OF THERMAL EXPANSION
Granted: September 26, 2024
Application Number:
20240321636
The present technology includes semiconductor processing methods and devices with improved expansion of the bulk material in substrate features. Methods include cleaning a substrate that is formed from silicon oxide and that defines one or more features and that includes a liner that extends across the silicon oxide and within one or more features and a copper-containing layer deposited on the liner and extending within the one or more features. Methods include depositing a second metal…
ULTRA-THIN LAYERS BY SELECTIVE PASSIVATION
Granted: September 26, 2024
Application Number:
20240321633
Methods for depositing ultra-thin films are disclosed. Some embodiments of the disclosure utilize ultra-thin films as barrier layers, liner layers, or nucleation layers to decrease interconnect resistance. Some embodiments advantageously provide continuous films with thicknesses of less than or equal to about 20 ?. Some embodiments advantageously provide films with decreased roughness.
SELECTIVE OXIDATION PROCESSES FOR GATE-ALL-AROUND TRANSISTORS
Granted: September 26, 2024
Application Number:
20240321584
Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example,…
FACEPLATE LOADING PLATFORM
Granted: September 19, 2024
Application Number:
20240312815
Exemplary semiconductor component assembly platforms include a base frame having a frame body extending from a first end to a second end. The component assembly platforms include a telescoping frame movably connected to the base frame and a component support movably connected to the telescoping frame. Semiconductor component assembly platforms exhibit a compressed position and a fully extended position. In a compressed position, a first end of the telescoping frame is disposed…
MEMORY STRUCTURE WITH 4F2 OPTIMIZED CELL LAYOUT
Granted: September 19, 2024
Application Number:
20240315004
A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate…
HIGH VOLTAGE NOISE CANCELLATION
Granted: September 19, 2024
Application Number:
20240313725
A high voltage noise reduction unit that includes (i) an input that is configured to receive a high voltage input signal (HVIS); (ii) a positive isolated supply unit that is configured to receive the HVIS and to output a positive supply signal that floats on the HVIS; (iii) a negative isolated supply unit that is configured to receive the HVIS and to output a negative supply signal that floats on the HVIS; (iv) a low pass filter that is configured to filter the HVIS to provide a filtered…
SEMICONDUCTOR DEVICES CONTAINING BI-METALLIC SILICIDE WITH REDUCED CONTACT RESISTIVITY
Granted: September 19, 2024
Application Number:
20240313079
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a bi-metallic silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The bi-metallic silicide layer includes a first metal, a second metal different than the first metal, and a silicon containing compound, and includes greater…
