MEMORY STRUCTURE WITH 4F2 OPTIMIZED CELL LAYOUT
Granted: September 19, 2024
Application Number:
20240315004
A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate…
METHOD FOR DETECTION OF WAFER SLIPPAGE
Granted: September 19, 2024
Application Number:
20240308019
Exemplary methods for detecting substrate slippage include sweeping a first sensor and a second sensor of an in-situ monitoring system across the substrate as the substrate undergoes polishing with a rotatable platen. A first sequence of signal values from the first sensor and a second sequence of signal values from the second sensor include a signal strength relative to the thickness of the layer. For each signal value of at least some of the first sequence of signal values and second…
CONTACT CONSTRUCTION FOR SEMICONDUCTOR DEVICES WITH LOW-DIMENSIONAL MATERIALS
Granted: September 12, 2024
Application Number:
20240306391
Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to…
HYDROGEN PLASMA TREATMENT FOR FORMING LOGIC DEVICES
Granted: September 12, 2024
Application Number:
20240304495
A method of forming a semiconductor device structure by utilizing a hydrogen plasma treatment to promote selective deposition is disclosed. In some embodiments, the method includes forming a metal layer within at least one feature on the semiconductor device structure. The method includes exposing the metal layer to a hydrogen plasma treatment. The hydrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to…
HEATER ASSEMBLY WITH PROCESS GAP CONTROL FOR BATCH PROCESSING CHAMBERS
Granted: September 12, 2024
Application Number:
20240304470
A heater assembly having a top seal and a second seal configured to account for deviation in processing heights and motor runoff of a heater standoff. The top seal is positioned between a shield plate and a top plate and the bottom seal is positioned between a heater mounting base and the heater standoff.
SEMICONDUCTOR CHAMBER COMPONENTS WITH ADVANCED COATING TECHNIQUES
Granted: September 12, 2024
Application Number:
20240304423
The present technology is generally directed to semiconductor processing systems and methods. Systems and methods include a chamber having a plurality of chamber components, such as a pedestal, a lid stack, a faceplate, electrode, and a showerhead. The faceplate is supported with the lid stack and defines a plurality of first apertures and the showerhead is positioned between the faceplate and the pedestal and defines a plurality of second apertures. In systems and methods, the…
METAL ORGANONITRILE PRECURSORS FOR THIN FILM DEPOSITION
Granted: September 12, 2024
Application Number:
20240301549
Metal complexes with nitrile ligands of the type MO2X2L2, where M is molybdenum or tungsten, X is a halogen, each L is independently an organonitrile ligand with the general formula NCR, where each R is independently a C2-C18 group. Metal complexes with dinitrile bidentate ligands of the type MO2X2L?, where L? is a dintrile ligand, and dinitrile bridging ligands of the type (MO2X2)2L?, where L? is a dinitrile bridging ligand connecting the two metal atoms. Methods of making and using the…
NANOFILTRATION FOR WAFER RINSING
Granted: September 5, 2024
Application Number:
20240295046
The present technology includes methods for rinsing an electroplating apparatus, a component thereof, and/or a substrate. The method includes removing at least a portion of a bath solution having a first pH from an electroplating bath. The method includes filtering the removed bath solution through a nanofiltration membrane, forming a permeating containing a recycled rinse agent, and a retentate. The method includes transferring the recycled rinse agent to the one or more nozzles and…
METHODS OF FORMING INTERCONNECT STRUCTURES
Granted: September 5, 2024
Application Number:
20240297073
Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface…
APPARATUS AND TECHNIQUES FOR SUBSTRATE PROCESSING USING INDEPENDENT ION SOURCE AND RADICAL SOURCE
Granted: September 5, 2024
Application Number:
20240297016
A system may include a substrate stage to support a substrate, and a plurality of beam sources. The plurality of beam sources may include an ion beam source, the ion beam source arranged to direct an ion beam to the substrate, and a radical beam source, the radical beam source arranged to direct a radical beam to the substrate. The system may include a controller configured to control the ion beam source and the radical beam source to operate independently of one another, in at least one…
METHODS FOR FORMING IMPURITY FREE METAL ALLOY FILMS
Granted: August 29, 2024
Application Number:
20240287678
Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5,…
DRAM Transistor Including Buried Bitline
Granted: August 29, 2024
Application Number:
20240292599
Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source/drain formed beneath the plurality of pillars, and a contact formed…
STRESS INCORPORATION IN SEMICONDUCTOR DEVICES
Granted: August 29, 2024
Application Number:
20240290884
The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the…
VOID-FREE STRESS INCORPORATION IN SEMICONDUCTOR DEVICES
Granted: August 29, 2024
Application Number:
20240290883
The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the…
TWO LEVEL VACUUM WAFER TRANSFER SYSTEM WITH ROBOTS ON EACH LEVEL
Granted: August 29, 2024
Application Number:
20240290644
Exemplary semiconductor processing systems may include a first processing chamber and a second processing chamber. Each processing chamber may define a processing region and a transfer region having a slit valve. Each processing chamber may include a substrate support that is vertically translatable between the processing region and the transfer region. Each processing chamber may include a gas delivery assembly disposed above and in alignment with the substrate support. The first…
DEPOSITION OR ETCH CHAMBER WITH COMPLETE SYMMETRY AND HIGH TEMPERATURE SURFACES
Granted: August 29, 2024
Application Number:
20240290638
Exemplary semiconductor processing systems may include a chamber having a body having a sidewall and a base. The chamber may include a pumping liner atop the body and a faceplate atop the pumping liner. The chamber may include a substrate support. The substrate support may include a plate and a shaft. The chamber may include a seal plate coupled with the shaft below the plate. The seal plate may have a greater diameter than the plate. The seal plate may include an RF gasket outward of…
PROCESSING METHODS TO IMPROVE ETCHED SILICON-AND-GERMANIUM-CONTAINING MATERIAL SURFACE ROUGHNESS
Granted: August 29, 2024
Application Number:
20240290623
Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the pre-treatment precursor in the remote plasma system. The methods may include flowing plasma effluents of the pre-treatment precursor to a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be…
SYSTEMS AND METHODS FOR DEPOSITING LOW-K DIELECTRIC FILMS
Granted: August 29, 2024
Application Number:
20240290611
Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-oxygen-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency less than 15 MHz (e.g., 13.56 MHz).…
MOVEABLE SUPPORT TO SECURE ELECTRICALLY CONDUCTIVE AND NONCONDUCTIVE SAMPLES IN A VACUUM CHAMBER
Granted: August 29, 2024
Application Number:
20240290572
A chuck that supports a sample in a processing chamber and comprises: a support plate formed from a dielectric material, the support plate including an upper planar support surface sized and shaped to retain a substrate disposed on the support plate; one or more electrodes disposed within the support plate proximate the upper planar support surface; a plurality of lift pin holes formed completely through the support plate; a plurality of stub cavities formed within the support plate,…
METHODS OF REDUCING OR ELIMINATING DEPOSITS IN AN ELECTROPLATING SYSTEM
Granted: August 29, 2024
Application Number:
20240287702
The present technology includes methods for reducing the formation of insoluble deposits in a plating system or a surface thereof. The methods include reducing a volume of a plating solution having a first pH in a plating bath from a first volume to a second volume, adding a replenishment agent to the plating solution to increase the volume of the plating solution from the second volume to the first volume. The replenishment agent is characterized by a second pH, where the second pH…
