CHAMBER COMPONENT FOR IMPROVED CLEANING EFFICIENCY
Granted: February 13, 2025
Application Number:
20250051910
A pre-heat ring and a process chamber having the same are described herein. In one example, a process chamber for film deposition comprises a chamber volume, a substrate support disposed in the chamber volume, the substrate support having a radially outward surface, and a pre-heat ring surrounding the substrate support. The pre-heat ring comprises a tapered wall facing the radially outward surface. The tapered wall narrows towards a top surface of the pre-heat ring and towards the…
METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERS
Granted: February 13, 2025
Application Number:
20250056871
Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.
SEMICONDUCTOR SUBSTRATE SUPPORT LEVELING APPARATUS
Granted: February 13, 2025
Application Number:
20250054797
Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The chamber body may define an interior volume. The systems may include a substrate support extending through the base of the chamber body. The substrate support may be configured to support a substrate within the interior volume. The systems may include a faceplate positioned within the interior volume of the chamber body. The faceplate may define a plurality of apertures through the…
METHODS OF ETCHING OXYGEN-CONTAINING FEATURES AT LOW TEMPERATURES
Granted: February 13, 2025
Application Number:
20250054770
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of oxygen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The methods may include contacting the substrate…
METHODS OF ETCHING CARBON-CONTAINING FEATURES AT LOW TEMPERATURES
Granted: February 13, 2025
Application Number:
20250054768
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor and a sulfur-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of carbon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. The methods may include contacting the substrate with…
RF PULSING ASSISTED LOW-K FILM DEPOSITION WITH HIGH MECHANICAL STRENGTH
Granted: February 13, 2025
Application Number:
20250054749
Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by a pulsing RF power operating at less than or about 2,000 W. The methods may include…
ADHESION IMPROVEMENTS IN METAL-CONTAINING HARDMASKS
Granted: February 13, 2025
Application Number:
20250054748
Exemplary methods of semiconductor processing may include providing a treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include contacting a surface of the substrate with the treatment precursor. The methods may include providing deposition precursors to the processing region. The deposition precursors may include a metal-containing precursor. The methods may include forming plasma…
METHOD TO MORE PRECISELY CALIBRATE THE MECHANICAL TILT AND ROTATION ANGLES OF AN SEM COLUMN
Granted: February 13, 2025
Application Number:
20250054726
A method of determining a depth of a feature formed in a first region of a sample, by: positioning a test structure with known dimensions in a processing chamber having a charged particle column tilted at a first tilt angle and first rotational angle; determining the first tilt angle and first rotational angle by: taking an image of the test structure with the charged particle column tilted at the first tilt angle and the first rotational angle, measuring, based on the image, distances…
IMPROVED ADHESION LAYER IN FLEXIBLE COVERLENS
Granted: February 13, 2025
Application Number:
20250052928
Exemplary flexible coverlenses and the methods of making them are described. The methods may include exposing a surface of a substrate layer to a surface treatment plasma to form a treated surface of the substrate layer. A silicon-containing adhesion layer may be deposited on the treated surface of the substrate layer. A silane-containing adhesion promoter may be incorporated on the silicon-containing adhesion layer. The method may also include forming a hardcoat layer on the…
PLATING AND DEPLATING CURRENTS FOR MATERIAL CO-PLANARITY IN SEMICONDUCTOR PLATING PROCESSES
Granted: February 13, 2025
Application Number:
20250051951
A method of plating substrates may include placing a substrate in a plating chamber comprising a liquid, and applying a current to the liquid in the plating chamber to deposit a metal on exposed portions of the substrate, where the current may include alternating cycles of a forward plating current and a reverse deplating current. To determine the current characteristics, a model of a substrate may be simulated during the plating process to generate data points that relate…
METHODS OF FORMING ELECTRONIC DEVICES HAVING A STRAINED TRANSISTOR CHANNEL
Granted: February 6, 2025
Application Number:
20250048683
Embodiments of the disclosure provide methods of manufacturing electronic devices that meet compressive stress requirements for PMOS transistors and tensile stress requirements for NMOS transistors. Each P-metal stack and P-metal stack: is formed on a top surface of a channel located between a source and a drain on a semiconductor substrate, and comprises nanosheet channel layers and trenches between each nanosheet channel layer, and has at least one side defining a gate trench. Some…
DIELECTRIC SPECTROSCOPY TEMPERATURE MONITORING USING ELECTROSTATIC CHUCK
Granted: February 6, 2025
Application Number:
20250046640
A method and a system for determining a temperature of a substrate using a dielectric spectroscopy system. One or more impedance signals are received, where the impedance signals are generated by the substrate and one or more components of the dielectric spectroscopy system in response to one or more measurement signals. At least one first impedance signal is associated with one or more impedance signals generated by the substrate. At least one second impedance signal is associated with…
CONCURRENT OR CYCLICAL ETCH AND DIRECTIONAL DEPOSITION
Granted: February 6, 2025
Application Number:
20250046601
An etching and deposition system including a process chamber containing a platen for supporting a substrate, an reactive-ion etching (RIE) source adapted to produce an ion beam and to direct the ion beam into the process chamber for etching the substrate, a first plasma enhanced chemical vapor deposition (PECVD) source located on a first side of the RIE source, the first PECVD source adapted to produce a first radical beam and to direct the first radical beam into the process chamber for…
TITANIUM NITRIDE GAPFILL PROCESSES FOR SEMICONDUCTOR DEVICES
Granted: February 6, 2025
Application Number:
20250046600
One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of…
METHODS OF FORMING ABRUPT INTERFACES BETWEEN SILICON-AND-CARBON-CONTAINING MATERIALS AND SILICON-AND-OXYGEN-CONTAINING MATERIALS
Granted: January 30, 2025
Application Number:
20250037987
Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing…
HIGH-TEMPERATURE IMPLANT FOR GATE-ALL-AROUND DEVICES
Granted: January 30, 2025
Application Number:
20250040186
Approaches herein provide devices and methods for forming gate-all-around transistors with improved gate spacer k-values. One method may include forming a gate-all-around (GAA) stack including a plurality of alternating first layers and second layers, and forming a source/drain (S/D) cavity through the plurality of alternating first layers and second layers. The method may further include forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and…
GROWTH CHAMBER SMART SEASONING
Granted: January 30, 2025
Application Number:
20250038053
A method of analyzing completion of seasoning of semiconductor processing chambers may include training a model using seasoning cycle characteristics data obtained from existing semiconductor processing chambers. A supervised learning process may label the characteristics data based on expert determined identify seasoning completion and may optionally label the characteristics data based on chamber open event information or preventive maintenance information. The trained model may be…
SiC TRENCH BOTTOM CORNER ROUNDING
Granted: January 30, 2025
Application Number:
20250038000
Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering…
EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE
Granted: January 30, 2025
Application Number:
20250037997
A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.
SEAM REMOVAL IN HIGH ASPECT RATIO GAP-FILL
Granted: January 30, 2025
Application Number:
20250037996
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the…
