METHODS OF FORMING ABRUPT INTERFACES BETWEEN SILICON-AND-CARBON-CONTAINING MATERIALS AND SILICON-AND-OXYGEN-CONTAINING MATERIALS
Granted: January 30, 2025
Application Number:
20250037987
Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing…
MULTI-PORT CROSS FLOW SYSTEM
Granted: January 30, 2025
Application Number:
20250037980
A processing chamber and port adaptor are provided. Processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. The processing chamber includes a port adapter coupled to the second end of the chamber body. The port adapter includes a body defining a plurality of apertures in fluid…
GAS DISTRIBUTION ASSEMBLIES FOR SEMICONDUCTOR DEVICES
Granted: January 30, 2025
Application Number:
20250037978
Gas distribution assemblies for semiconductor devices are described. The gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. The at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. Some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. Some embodiments of the gas distribution assemblies provide for reduced jetting on a…
PROCESS STACK FOR CVD PLASMA TREATMENT
Granted: January 30, 2025
Application Number:
20250037976
Gas distribution assemblies, processing chambers, and methods for processing substrates are provided. A substrate processing chamber includes a chamber body having a first end and a second end, a lid coupled to the first end of the chamber body, an isolator disposed on an upper surface of the lid, a faceplate disposed on an upper surface of the isolator, a substrate support disposed on a shaft extending through the second end of the chamber body, a pumping ring positioned within the…
Actively Controlled gas inject FOR PROCESS Temperature CONTROL
Granted: January 30, 2025
Application Number:
20250037975
A flow apparatus and process chamber having the same are described herein. In one example, flow apparatus for use in semiconductor processing comprises an inject assembly and an inductive heater coupled to the inject assembly. The inject assembly comprises an inject body, a first gas inlet configured to flow a first gas through the inject body, and a plurality of flow channels disposed in the inject body, the plurality of flow channels coupled to the first gas inlet. The inductive heater…
CHAMBER FOR SUBSTRATE BACKSIDE AND BEVEL DEPOSITION
Granted: January 30, 2025
Application Number:
20250037974
Disclosed herein is a processing system. The processing system has an upper chamber body and a lower chamber body defining a processing environment. An upper heater is moveably disposed in the upper chamber body. The upper heater has a moveable support and an upper step formed along an outer perimeter. A lower showerhead is fixedly disposed in the lower chamber body. The lower showerhead includes a top surface configured to support a substrate, a lower step disposed along an outer…
INTEGRATED PLASMA CLEAN AND DIELECTRIC PASSIVATION DEPOSITION PROCESSES
Granted: January 23, 2025
Application Number:
20250029835
Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The…
Low Resistance and High Reliability Metallization Module
Granted: January 23, 2025
Application Number:
20250029874
Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.
SHAPED FACEPLATE FOR EXTREME EDGE FILM UNIFORMITY
Granted: January 23, 2025
Application Number:
20250029849
Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support within the chamber body. The substrate support may define a substrate support surface. The chambers may include a faceplate supported atop the chamber body. The substrate support and a bottom surface of the faceplate may at least partially define a processing region. The bottom surface of the faceplate may define an annular protrusion that is directly above at least a…
SELECTIVE ETCHING BETWEEN SILICON-AND-GERMANIUM-CONTAINING MATERIALS WITH VARYING GERMANIUM CONCENTRATIONS
Granted: January 23, 2025
Application Number:
20250029841
Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing region of a semiconductor processing chamber. A first layer of silicon-and-germanium-containing material and a second layer of silicon-and-germanium-containing material may be disposed on a substrate housed within the processing region. A native oxide may be present on the first layer and the second layer. The methods may include contacting the substrate with the pre-treatment…
HEATED METAL LID FOR SELECTIVE PECVD
Granted: January 23, 2025
Application Number:
20250029816
Gas distribution assemblies for a semiconductor manufacturing processing chamber comprising a first showerhead with a first flange and a second showerhead with a second flange. A first two-piece RF isolator comprises a first inner RF isolator spaced from a first outer RF isolator. The first inner RF isolator spaced from the first flange of the first showerhead to create a first flow path. A second two-piece RF isolator comprises a second inner RF isolator spaced from a second outer RF…
SEMICONDUCTOR CHEMICAL PRECURSOR WITH GAS PASSAGES
Granted: January 23, 2025
Application Number:
20250027199
Ampoules including a solid volume of the semiconductor chemical precursor and methods of use and manufacturing are described. The solid volume of the semiconductor chemical precursor includes an ingress opening, at least one flow channel, and an outlet passage that are in fluid communication with each other. The solid volume of the semiconductor manufacturing precursor is made of a porous or alternatively a non-porous material. A flow path is defined by at least one flow channel through…
OLED ANODE STRUCTURES INCLUDING AMORPHOUS TRANSPARENT CONDUCTING OXIDES AND OLED PROCESSING METHOD COMPRISING THE SAME
Granted: January 16, 2025
Application Number:
20250024693
Exemplary methods of OLED device processing are described. The methods may include forming an anode on a substrate. Forming the anode may include forming a first metal oxide material on the substrate, forming a metal layer over the first metal oxide material, forming a protective barrier over the metal layer, and forming a second metal oxide material over the amorphous protection material. The protective barrier may be an amorphous protection material overlying the metal layer.
SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY
Granted: January 16, 2025
Application Number:
20250022935
Methods of manufacturing memory devices are provided. The method comprises forming a first epitaxial layer on a substrate; and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of an oxide material and a metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a fill material adjacent to the at least one memory cell.
METHODS OF FORMING INTERCONNECT STRUCTURES
Granted: January 16, 2025
Application Number:
20250022750
Embodiments of the disclosure provide methods of forming interconnect structures in the manufacture of microelectronic devices. In one or more embodiments, microelectronic devices described herein comprise at least one top interconnect structure that is interconnected to at least one bottom interconnect structure. Embodiments of the disclosure relate to methods of improving barrier layer and metal liner properties in the interconnect structures without increasing capacitance and/or…
CYCLIC ETCH OF SILICON OXIDE AND SILICON NITRIDE
Granted: January 16, 2025
Application Number:
20250022714
Exemplary semiconductor processing methods may include flowing a fluorine-containing precursor and a hydrogen-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may include forming plasma effluents of the fluorine-containing precursor and the…
DIRECTIONAL SELECTIVE FILL OF SILICON OXIDE MATERIALS
Granted: January 16, 2025
Application Number:
20250022704
Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature. The methods may include forming plasma effluents of the silicon-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The methods may include providing an oxygen-containing precursor to the processing region,…
PLASMA SYSTEM HAVING RESIDENCE TIME TUNING ASSEMBLY
Granted: January 16, 2025
Application Number:
20250022697
A plasma processing apparatus. The plasma processing apparatus may include a plasma chamber, to define a plasma therein, and an extraction aperture, arranged along a first side of the plasma chamber, the extraction aperture to define an ion beam extracted therethrough. The plasma processing apparatus may further include a residence time tuning assembly, coupled to a portion of the plasma chamber, different from the first side, wherein the residence time tuning assembly comprises a…
COOLING FRAME FOR DIFFUSER
Granted: January 16, 2025
Application Number:
20250019824
Exemplary substrate processing chambers may include a chamber body defining a processing region. The chambers may include a backing plate disposed atop the chamber body, a diffuser above the processing region and supported by the backing plate, and a cooling frame disposed between the backing plate and the diffuser. The cooling frame may be coupled with the diffuser. The cooling frame may include a body having one or more fluid inlets and one or more fluid outlets. The body may define an…
GASBOX FOR SEMICONDUCTOR PROCESSING CHAMBER
Granted: January 9, 2025
Application Number:
20250014914
Exemplary semiconductor processing chambers may include a gasbox including a first plate having a first surface and a second surface opposite to the first surface. The first plate of the gasbox may define a central aperture that extends from the first surface to the second surface. The first plate may define an annular recess in the second surface. The first plate may define a plurality of apertures extending from the first surface to the annular recess in the second surface. The gasbox…
