METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERS
Granted: February 13, 2025
Application Number:
20250056871
Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.
RF PULSING ASSISTED LOW-K FILM DEPOSITION WITH HIGH MECHANICAL STRENGTH
Granted: February 13, 2025
Application Number:
20250054749
Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by a pulsing RF power operating at less than or about 2,000 W. The methods may include…
METHODS OF FORMING ELECTRONIC DEVICES HAVING A STRAINED TRANSISTOR CHANNEL
Granted: February 6, 2025
Application Number:
20250048683
Embodiments of the disclosure provide methods of manufacturing electronic devices that meet compressive stress requirements for PMOS transistors and tensile stress requirements for NMOS transistors. Each P-metal stack and P-metal stack: is formed on a top surface of a channel located between a source and a drain on a semiconductor substrate, and comprises nanosheet channel layers and trenches between each nanosheet channel layer, and has at least one side defining a gate trench. Some…
DIELECTRIC SPECTROSCOPY TEMPERATURE MONITORING USING ELECTROSTATIC CHUCK
Granted: February 6, 2025
Application Number:
20250046640
A method and a system for determining a temperature of a substrate using a dielectric spectroscopy system. One or more impedance signals are received, where the impedance signals are generated by the substrate and one or more components of the dielectric spectroscopy system in response to one or more measurement signals. At least one first impedance signal is associated with one or more impedance signals generated by the substrate. At least one second impedance signal is associated with…
CONCURRENT OR CYCLICAL ETCH AND DIRECTIONAL DEPOSITION
Granted: February 6, 2025
Application Number:
20250046601
An etching and deposition system including a process chamber containing a platen for supporting a substrate, an reactive-ion etching (RIE) source adapted to produce an ion beam and to direct the ion beam into the process chamber for etching the substrate, a first plasma enhanced chemical vapor deposition (PECVD) source located on a first side of the RIE source, the first PECVD source adapted to produce a first radical beam and to direct the first radical beam into the process chamber for…
TITANIUM NITRIDE GAPFILL PROCESSES FOR SEMICONDUCTOR DEVICES
Granted: February 6, 2025
Application Number:
20250046600
One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of…
EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE
Granted: January 30, 2025
Application Number:
20250037997
A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.
HIGH-TEMPERATURE IMPLANT FOR GATE-ALL-AROUND DEVICES
Granted: January 30, 2025
Application Number:
20250040186
Approaches herein provide devices and methods for forming gate-all-around transistors with improved gate spacer k-values. One method may include forming a gate-all-around (GAA) stack including a plurality of alternating first layers and second layers, and forming a source/drain (S/D) cavity through the plurality of alternating first layers and second layers. The method may further include forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and…
GROWTH CHAMBER SMART SEASONING
Granted: January 30, 2025
Application Number:
20250038053
A method of analyzing completion of seasoning of semiconductor processing chambers may include training a model using seasoning cycle characteristics data obtained from existing semiconductor processing chambers. A supervised learning process may label the characteristics data based on expert determined identify seasoning completion and may optionally label the characteristics data based on chamber open event information or preventive maintenance information. The trained model may be…
SiC TRENCH BOTTOM CORNER ROUNDING
Granted: January 30, 2025
Application Number:
20250038000
Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering…
SEAM REMOVAL IN HIGH ASPECT RATIO GAP-FILL
Granted: January 30, 2025
Application Number:
20250037996
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the…
SEQUENTIAL PLASMA AND THERMAL TREATMENT
Granted: January 30, 2025
Application Number:
20250037989
Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch…
METHODS OF FORMING ABRUPT INTERFACES BETWEEN SILICON-AND-CARBON-CONTAINING MATERIALS AND SILICON-AND-OXYGEN-CONTAINING MATERIALS
Granted: January 30, 2025
Application Number:
20250037987
Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing…
MULTI-PORT CROSS FLOW SYSTEM
Granted: January 30, 2025
Application Number:
20250037980
A processing chamber and port adaptor are provided. Processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. The processing chamber includes a port adapter coupled to the second end of the chamber body. The port adapter includes a body defining a plurality of apertures in fluid…
GAS DISTRIBUTION ASSEMBLIES FOR SEMICONDUCTOR DEVICES
Granted: January 30, 2025
Application Number:
20250037978
Gas distribution assemblies for semiconductor devices are described. The gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. The at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. Some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. Some embodiments of the gas distribution assemblies provide for reduced jetting on a…
PROCESS STACK FOR CVD PLASMA TREATMENT
Granted: January 30, 2025
Application Number:
20250037976
Gas distribution assemblies, processing chambers, and methods for processing substrates are provided. A substrate processing chamber includes a chamber body having a first end and a second end, a lid coupled to the first end of the chamber body, an isolator disposed on an upper surface of the lid, a faceplate disposed on an upper surface of the isolator, a substrate support disposed on a shaft extending through the second end of the chamber body, a pumping ring positioned within the…
Actively Controlled gas inject FOR PROCESS Temperature CONTROL
Granted: January 30, 2025
Application Number:
20250037975
A flow apparatus and process chamber having the same are described herein. In one example, flow apparatus for use in semiconductor processing comprises an inject assembly and an inductive heater coupled to the inject assembly. The inject assembly comprises an inject body, a first gas inlet configured to flow a first gas through the inject body, and a plurality of flow channels disposed in the inject body, the plurality of flow channels coupled to the first gas inlet. The inductive heater…
CHAMBER FOR SUBSTRATE BACKSIDE AND BEVEL DEPOSITION
Granted: January 30, 2025
Application Number:
20250037974
Disclosed herein is a processing system. The processing system has an upper chamber body and a lower chamber body defining a processing environment. An upper heater is moveably disposed in the upper chamber body. The upper heater has a moveable support and an upper step formed along an outer perimeter. A lower showerhead is fixedly disposed in the lower chamber body. The lower showerhead includes a top surface configured to support a substrate, a lower step disposed along an outer…
INTEGRATED PLASMA CLEAN AND DIELECTRIC PASSIVATION DEPOSITION PROCESSES
Granted: January 23, 2025
Application Number:
20250029835
Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The…
SHAPED FACEPLATE FOR EXTREME EDGE FILM UNIFORMITY
Granted: January 23, 2025
Application Number:
20250029849
Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support within the chamber body. The substrate support may define a substrate support surface. The chambers may include a faceplate supported atop the chamber body. The substrate support and a bottom surface of the faceplate may at least partially define a processing region. The bottom surface of the faceplate may define an annular protrusion that is directly above at least a…
