SILICON CARBIDE TRANSISTOR WITH CHANNEL COUNTER-DOPING AND POCKET-DOPING
Granted: August 1, 2024
Application Number:
20240258375
A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be…
METHODS OF FORMING INTERCONNECT STRUCTURES
Granted: August 1, 2024
Application Number:
20240258164
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A pre-clean process is performed before a self-assembled monolayer (SAM) is formed on the bottom of the gap. A barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. The SAM is removed after selectively depositing the barrier layer on the sidewalls.
METHODS OF FORMING INTERCONNECT STRUCTURES
Granted: August 1, 2024
Application Number:
20240258161
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap which resists degradation when exposed to the ambient atmosphere. A barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. The SAM is removed after selectively depositing the barrier layer on the sidewalls.
APPARATUS AND METHODS FOR SEMICONDUCTOR PROCESSING
Granted: August 1, 2024
Application Number:
20240258153
Described are apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. The wafer is subjected to a pressure differential between the top surface and bottom surface so that sufficient force prevents the wafer from moving during processing, the pressure differential generated by applying a decreased pressure to the back side of the wafer.
SUBSTRATE PROCESSING FOR AlN AND GaN POLARITY CONTROL
Granted: August 1, 2024
Application Number:
20240258106
The present technology includes semiconductor structures. Structures include a silicon-containing substrate, a layer of metal nitride overlying the silicon-containing substrate, a structure overlying the layer of the metal nitride, and an oxygen rich layer disposed between the layer of the metal nitride and the structure. The structure is formed from a material that includes a gallium-containing material, and aluminum nitride material, or a combination thereof, where at least about 90…
PLASMA TREATMENT OF BARRIER AND LINER LAYERS
Granted: August 1, 2024
Application Number:
20240258103
Embodiments of the disclosure relate to methods for forming electrical interconnects. Additional embodiments provide methods of forming and treating barrier and liner layers to improve film and material properties. In some embodiments, the resulting composite layers provide improved resistivity, decrease void formation and improve device reliability.
SURFACE ROUGHNESS REDUCTION FOR PHOTONICS USING HIGH-TEMPERATURE IMPLANTATION
Granted: August 1, 2024
Application Number:
20240255700
Disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. One method includes providing a workpiece including a contact etch stop layer (CESL) over a device layer, patterning the CESL to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. The method may further include directing ions into an upper surface of the waveguide…
NON-DESTRUCTIVE CLASSIFICATION OF SPECIMENS BASED ON ENERGY SIGNATURE MEASUREMENTS
Granted: August 1, 2024
Application Number:
20240255449
Disclosed herein is a system for non-destructive classification of specimens. The system includes an e-beam source, an X-ray measurement module, and a computational module. The e-beam source is configured to project e-beams on a specimen at one or more e-beam landing energies, so as to penetrate the specimen and induce emission of X-rays. The X-ray measurement module is configured to measure the emitted X-rays. The computational module is configured to process the measurement data to…
EPI ISOLATION PLATE AND PARALLEL BLOCK PURGE FLOW TUNING FOR GROWTH RATE AND UNIFORMITY
Granted: August 1, 2024
Application Number:
20240254655
A method and apparatus for processing substrates suitable for use in semiconductor manufacturing. The method includes heating a substrate positioned on a substrate support. The method includes flowing a purge gas over an isolation plate disposed above the substrate, the flowing the purge gas including diverting a portion of the purge gas below the isolation plate through a plurality of perforations in the isolation plate. The method includes flowing one or more process gases over the…
DRAM Transistor Including Pillars Formed Using Low-Temperature Ion Implant
Granted: July 25, 2024
Application Number:
20240251546
Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). In one approach, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. The method may further include forming a contact by directing second ions into an upper surface of the…
DRY ETCH OF BORON-CONTAINING MATERIAL
Granted: July 25, 2024
Application Number:
20240249953
Exemplary methods of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The methods may include generating plasma effluents of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluents of the…
BIPOLAR ELECTROSTATIC CHUCK ELECTRODE DESIGNS
Granted: July 25, 2024
Application Number:
20240249924
Exemplary substrate support assemblies may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a first bipolar electrode embedded within the electrostatic chuck body. The assemblies may include a second bipolar electrode embedded within the electrostatic chuck body. An entirety of the second bipolar electrode may be radially…
Processing Chamber With Multiple Plasma Units
Granted: July 25, 2024
Application Number:
20240249918
Provided is a processing chamber configured to contain a semiconductor substrate in a processing region of the chamber. The processing chamber includes a remote plasma unit and a direct plasma unit, wherein one of the remote plasma unit or the direct plasma unit generates a remote plasma and the other of the remote plasma unit or the direct plasma unit generates a direct plasma. The combination of a remote plasma unit and a direct plasma unit is used to remove, etch, clean, or treat…
FILLING EMPTY STRUCTURES BY DEPOSITION UNDER SEM - BALANCING PARAMETERS BY GAS FLOW CONTROL
Granted: July 25, 2024
Application Number:
20240249909
A method of evaluating, with an evaluation tool that includes a first charged particle column, a region of interest on a sample that includes an array of holes separated by solid portions, the method comprising: positioning the sample such that the region of interest is under a field of view of the first charged particle column; and locally depositing material within the array of holes in the region of interest by: pulsing a flow of deposition gas to the region of interest by turning the…
INDIUM-GALLIUM-NITRIDE LIGHT EMITTING DIODES WITH INCREASED QUANTUM EFFICIENCY
Granted: July 25, 2024
Application Number:
20240247407
Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region…
PRECURSOR DELIVERY SYSTEM FOR SEMICONDUCTOR DEVICE FORMATION
Granted: July 25, 2024
Application Number:
20240247374
Embodiments of precursor delivery systems are described herein. The precursor delivery systems include a reservoir having a cylindrical body, a conical shaped inlet on a first end of the cylindrical body, and a conical shaped outlet on a second end of the cylindrical body. Each of the conical shaped inlet and the conical shaped outlet independently have an angle in a range of from 5 degrees to 45 degrees. The amount of time to purge the reservoir described herein is reduced by at least…
ADJUSTABLE CROSS-FLOW PROCESS CHAMBER LID
Granted: July 25, 2024
Application Number:
20240247373
Apparatus and methods for improving deposition uniformity in a cross-flow processing chamber are described. A precursor inlet is configured to allow a cross-flow of precursor from the precursor inlet side of the lid to an exhaust side of the lid opposite a center of the lid from the precursor inlet side. At least one purge gas inlet is in fluid communication with a purge gas channel, the purge gas channel having at least one opening aligned to provide a flow of gas to a center of a…
SEMICONDUCTOR PROCESSING CHAMBERS AND METHODS FOR CLEANING THE SAME
Granted: July 25, 2024
Application Number:
20240247371
A processing chamber may include a gas distribution member, a substrate support, and a pumping liner. The gas distribution member and the substrate support may at least in part define a processing volume. The pumping liner may define an internal volume in fluid communication with the processing volume via a plurality of apertures of the pumping liner circumferentially disposed about the processing volume. The processing chamber may further include a flow control mechanism operable to…
LOW RESISTIVITY GAPFILL FOR LOGIC DEVICES
Granted: July 18, 2024
Application Number:
20240240314
Embodiments of the disclosure relate to methods for metal gapfill of a logic device with lower resistivity. Specific embodiments provide integrated separate tungsten PVD processes with plasma-etch to solve the overhang issue caused by tungsten PVD and the high resistivity caused by nucleation.
PHOTOLITHOGRAPHY ENHANCEMENT TECHNIQUES
Granted: July 18, 2024
Application Number:
20240242970
Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may include a photoresist material overlying a silicon-containing material. The photoresist material may define an aperture. The processing region may be at least partially defined above a substrate support on which the substrate is seated. The methods may include forming…
