High critical temperature metal nitride layer with oxide or oxynitride seed layer
Granted: December 31, 2024
Patent Number:
12185643
A superconducting device includes a substrate, a metal oxide or metal oxynitride seed layer on the substrate, and a metal nitride superconductive layer disposed directly on the seed layer. The seed layer is an oxide or oxynitride of a first metal, and the superconductive layer is a nitride of a different second metal.
Resonator, linear accelerator, and ion implanter having dielectric-free resonator chamber
Granted: December 31, 2024
Patent Number:
12185451
An apparatus may include a resonator chamber, arranged in a vacuum enclosure; an RF electrode assembly, arranged within the vacuum enclosure; and a resonator coil, disposed within the resonator chamber, the resonator coil having a high voltage end, directly connected to at least one RF electrode of the RF electrode assembly.
High-temperature substrate support assembly with failure protection
Granted: December 31, 2024
Patent Number:
12185433
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the…
Threshold voltage modulation for gate-all-around FET architecture
Granted: December 31, 2024
Patent Number:
12183798
A method of forming a gate stack structure includes forming a dipole metal layer on a high-? gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-? gate dielectric layer.
MOSFET gate shielding using an angled implant
Granted: December 31, 2024
Patent Number:
12183794
Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of…
Semiconductor device packaging methods
Granted: December 31, 2024
Patent Number:
12183684
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded dies therein. In certain embodiments, an insulating layer is formed over the…
Methods for copper doped hybrid metallization for line and via
Granted: December 31, 2024
Patent Number:
12183631
Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first…
In-situ semiconductor processing chamber temperature apparatus
Granted: December 31, 2024
Patent Number:
12183605
Methods and systems for in-situ temperature control are provided. The method includes delivering a temperature-sensing disc into a processing region of a processing chamber without breaking vacuum. The temperature-sensing disc includes one or more cameras configured to perform IR-based imaging. The method further includes measuring a temperature of at least one region of at least one chamber surface in the processing region of the processing chamber by imaging the at least one surface…
Methods of parallel transfer of micro-devices using treatment
Granted: December 24, 2024
Patent Number:
12176384
A method of transferring micro-devices includes selectively treating a first adhesive layer to form a treated portion and an untreated portion while micro-devices are attached the first adhesive layer. A second adhesive layer on a second surface is placed to abut the micro-devices. The first adhesive layer is exposed to illumination in a region that overlaps at least some of the treated portion and at least some of the untreated portion. Exposing the first adhesive layer to illumination…
Dual oxide analog switch for neuromorphic switching
Granted: December 24, 2024
Patent Number:
12178146
Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
Support ring for an interlocking process kit for a substrate processing chamber
Granted: December 24, 2024
Patent Number:
D1055006
Rotatable thermal processing chamber
Granted: December 24, 2024
Patent Number:
12176242
The present disclosure relates to heating a substrate in a rapid thermal processing (RTP) chamber. The chamber may contain a rotatable assembly configured to accommodate and rotate the substrate while a heat source inside the RTP chamber applies heat to the substrate. The rotatable assembly is partially disposed outside the RTP chamber. A seal may formed around the rotatable assembly and maintain a vacuum inside the RTP chamber while the rotatable assembly rotates. The rotatable assembly…
Method and chamber for backside physical vapor deposition
Granted: December 24, 2024
Patent Number:
12176205
Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to…
Magnetron design for improved bottom coverage and uniformity
Granted: December 24, 2024
Patent Number:
12176191
A magnet assembly for a magnetron of a processing chamber includes a support member. A plurality of magnetic tracks is mounted to the support member. Each magnetic track includes a pair of magnetic poles. A partial magnetic track is mounted to the support member. The partial magnetic track includes a single unpaired magnetic pole. The partial magnetic track is mounted proximal to a center of rotation of the support member.
Arc management algorithm of RF generator and match box for CCP plasma chambers
Granted: December 24, 2024
Patent Number:
12176190
Methods, apparatuses and systems for detecting and managing arc events during a plasma chamber process include receiving impedance data measured during a plasma chamber process, analyzing the impedance data to determine if an arc event is occurring during the plasma chamber process, and if it is determined that an arc event is occurring, an action is taken to suppress an arc of the arc event. In some instances, a machine learning model that has been trained to recognize when an arc event…
Optical spectrum sensor wafer or robot for chamber condition monitoring
Granted: December 24, 2024
Patent Number:
12176188
Embodiments disclosed herein include a diagnostic substrate. In an embodiment, the diagnostic substrate comprises a substrate, a circuit board on the substrate, and a spectrometer coupled to the circuit board. In an embodiment, the diagnostic substrate further comprises a processor on the circuit board and communicatively coupled to the spectrometer.
Gray level ratio inspection
Granted: December 24, 2024
Patent Number:
12175656
A method for gray level ratio inspection comprising: obtaining an electron image that comprises region of interest (ROI) pixels of a ROI of the sample and reference pixels of a reference region of the sample, where the ROI pixels are obtained by illuminating the ROI with the electron beam and the reference pixels are obtained without illuminating the reference region with an electron beam; calculating a reference dark level value based on values of at least some of the reference pixels;…
Fluid delivery mounting panel and system
Granted: December 24, 2024
Patent Number:
12173807
A system includes a mounting panel having diffusion-bonded metal plates that form a reservoir to contain a process fluid, multiple channels through which to flow the process fluid, and vias through which to flow the process fluid to and from process fluid control components attached to the mounting panel. At least a pair of the multiple channels are connected with the reservoir. A temperature sensor is attached to a top of the mounting panel, the temperature sensor in fluid communication…
High pressure oxidation of metal films
Granted: December 24, 2024
Patent Number:
12173413
Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.
Carrier head membrane with regions of different roughness
Granted: December 24, 2024
Patent Number:
12172264
An apparatus comprises a flexible membrane for use with a carrier head of a substrate chemical mechanical polishing apparatus. The membrane comprises an outer surface providing a substrate receiving surface, wherein the outer surface has a central portion and an edge portion surrounding the central portion, wherein the central portion has a first surface roughness and the edge portion has a second surface roughness, the first surface roughness being greater than the second surface…
