Spacer patterning process with flat top profile
Granted: January 28, 2025
Patent Number:
12211693
A method for forming a metal containing feature includes performing a deposition process, the deposition process comprising conformally depositing an over layer on top surfaces of a patterned mandrel layer and over a spacer layer on sidewalls of the patterned mandrel layer, and performing an etch process, the etch process comprising removing the over layer from the top surfaces of the patterned mandrel layer and shoulder portions of the spacer layer, and removing the shoulder portions of…
Copper, indium, gallium, selenium (CIGS) films with improved quantum efficiency
Granted: January 28, 2025
Patent Number:
12211947
A method includes forming, on a substrate by performing physical vapor deposition in vacuum, an absorber layer including copper (Cu), indium (In), gallium (Ga) and selenium (Se), forming a stack including the substrate and an oxygen-annealed absorber layer by performing in-situ oxygen annealing of the absorber layer to improve quantum efficiency of the image sensor by passivating selenium vacancies due to dangling bonds, and forming a cap layer over the oxygen-annealed absorber layer by…
Profile shaping for control gate recesses
Granted: January 28, 2025
Patent Number:
12211908
Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing…
Method of forming a metal liner for interconnect structures
Granted: January 28, 2025
Patent Number:
12211743
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
Flowable chemical vapor deposition of metal oxides
Granted: January 28, 2025
Patent Number:
12211736
Exemplary deposition methods may include introducing a vapor of a metal alkoxide into a processing volume of a semiconductor processing chamber. A substrate defining a trench may be housed in the processing volume. The methods may include condensing the vapor into a liquid metal alkoxide within the trench on the substrate. The methods may include forming a plasma external to the processing volume of the semiconductor processing chamber. The methods may include introducing…
Lift pin mechanism
Granted: January 28, 2025
Patent Number:
12211734
Methods and apparatus for a lift pin mechanism for substrate processing chambers are provided herein. In some embodiments, the lift pin mechanism includes a lift pin comprising a shaft with a top end, a bottom end, and a coupling end at the bottom end; a bellows assembly disposed about the shaft. The bellows assembly includes an upper bellows flange having an opening for axial movement of the shaft; a bellows having a first end coupled to a lower surface of the upper bellows flange such…
Electrostatic chuck design with improved chucking and arcing performance
Granted: January 28, 2025
Patent Number:
12211728
Aspects of the present disclosure relate to one or more implementations of a substrate support for a processing chamber. In one implementation, a substrate support includes a body having a center, and a support surface on the body configured to at least partially support a substrate. The substrate support includes a first angled wall that extends upward and radially outward from the support surface, and a first upper surface disposed above the support surface. The substrate support also…
Spatial pattern loading measurement with imaging metrology
Granted: January 28, 2025
Patent Number:
12211717
A method includes identifying first structure data of a first region of a substrate and receiving optical metrology data of the substrate associated with one or more substrate deposition processes in a processing chamber. The method further includes determining, based on the optical metrology data and the first structure data, a first growth rate of the first region of the substrate associated with the one or more substrate deposition processes. The method further includes predicting,…
Reconfigurable mainframe with replaceable interface plate
Granted: January 28, 2025
Patent Number:
12211714
A mainframe of a device fabrication system comprises a base and a plurality of facets on the base. Each facet of the plurality of facets comprises a frame. The mainframe further comprises a plurality of replaceable interface plates. Each replaceable interface plate of the plurality of replaceable interface plates is attached to a respective facet such that at most one replaceable interface plate is attached to each facet. At least one replaceable interface plate comprises one or more…
Ultra-high modulus and etch selectivity boron-carbon hardmask films
Granted: January 28, 2025
Patent Number:
12211694
Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a…
Uniformity control for plasma processing
Granted: January 28, 2025
Patent Number:
12211677
A system and method including a processing device. The processing device receives data including one or more plasma exposure durations of a plasma process. The plasma exposure duration are associated with a set of controlled elements. The processing device causes a each set of controlled elements to switch between a first mode of operation and a second mode of operation. Each set of controlled elements expose appropriate portion of a substrate to the plasma related fluxes. The first set…
Methods for shaping magnetic fields during semiconductor processing
Granted: January 21, 2025
Patent Number:
12203163
Methods of processing a substrate in a PVD chamber are provided herein. In some embodiments, a method of processing a substrate in a PVD chamber, includes: sputtering material from a target disposed in the PVD chamber and onto a substrate, wherein at least some of the material sputtered from the target is guided to the substrate through a magnetic field provided by one or more upper magnets disposed about a processing volume of the PVD chamber above a support pedestal for the substrate…
Methods and apparatus for hierarchical bitline for three-dimensional dynamic random-access memory
Granted: January 21, 2025
Patent Number:
12207458
Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate,…
Semiconductor processing chamber to accommodate parasitic plasma formation
Granted: January 21, 2025
Patent Number:
12205845
Exemplary processing systems may include a chamber body. The systems may include a pedestal configured to support a semiconductor substrate. The systems may include a faceplate. The chamber body, the pedestal, and the faceplate may define a processing region. The faceplate may be coupled with an RF power source. The systems may include a remote plasma unit. The remote plasma unit may be coupled at electrical ground. The systems may include a discharge tube extending from the remote…
Solid-state switch based high-speed pulser with plasma IEDF modification capability through multilevel output functionality
Granted: January 21, 2025
Patent Number:
12205797
Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having three MOSFETs and three series-connected capacitors. The capacitors are connected across a DC power supply and, depending on the value of the capacitors, voltage across each of them may be varied. Each of the top two capacitors is followed by a diode.…
Metal oxide resist patterning with electrical field guided post-exposure bake
Granted: January 21, 2025
Patent Number:
12204246
A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided…
Method and system for detecting anomalies in a semiconductor processing system
Granted: January 21, 2025
Patent Number:
12203828
The present disclosure relates to systems and methods for detecting anomalies in a semiconductor processing system. According to certain embodiments, one or more external sensors are mounted to a sub-fab component, communicating with the processing system via a communication channel different than a communication channel utilized by the sub-fab component and providing extrinsic sensor data that the sub-fab component is not configured to provide. The extrinsic sensor data may be combined…
Interference in-sensitive Littrow system for optical device structure measurement
Granted: January 21, 2025
Patent Number:
12203747
Embodiments described herein provide for devices and methods of measuring a pitch P of optical device structures and an orientation angle ? of the optical device structures. One embodiment of the system includes an optical arm coupled to an arm actuator. The optical arm includes a light source. The light source emits a light path operable to be diffracted to the stage. The optical arm further includes a first beam splitter and a second beam splitter positioned in the light path. The…
Batch curing chamber with gas distribution and individual pumping
Granted: January 21, 2025
Patent Number:
12203171
Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover…
Material deposition apparatus, method of depositing material on a substrate, and material deposition system
Granted: January 21, 2025
Patent Number:
12203164
A material deposition apparatus for depositing an evaporated material onto a substrate is provided. The material deposition apparatus includes a processing drum having a cooler configured to control a substrate temperature during processing of a substrate on the processing drum; a roller guiding the substrate towards the processing drum; a first heater assembly positioned to heat the substrate in a free-span area between the roller and the processing drum; a second heater assembly…
