Applied Materials Patent Grants

Porous plug bonding

Granted: September 24, 2024
Patent Number: 12097665
Embodiments described herein generally relate to porous plugs having sealing layers for use in substrate support pedestals and methods for forming the same. In one or more embodiments, the sealing layer can be formed in-situ by applying a fluoroelastomer composition to at least one of the porous plug and the walls of a cavity of an electrostatic chuck. The fluoroelastomer composition can be cured in-situ to form the sealing layer between the porous plug and the wall of the cavity. The…

Switchable delivery for semiconductor processing system

Granted: September 17, 2024
Patent Number: 12094689
Exemplary semiconductor processing systems may include a processing chamber including a lid stack having an output manifold. The systems may include a gas panel. The systems may include an input manifold. The input manifold may fluidly couple the gas panel with the output manifold of the processing chamber. A delivery line may extend from the input manifold to the output manifold. The systems may include a first transmission line extending from a first set of precursor sources of the gas…

Router architecture for multi-dimensional topologies in on-chip and on-package networks

Granted: September 17, 2024
Patent Number: 12095653
A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to…

Nitrogen-rich silicon nitride films for thin film transistors

Granted: September 17, 2024
Patent Number: 12094796
Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich…

Characterizing defects in semiconductor layers

Granted: September 17, 2024
Patent Number: 12094787
A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from…

Selective blocking of metal surfaces using bifunctional self-assembled monolayers

Granted: September 17, 2024
Patent Number: 12094766
Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, hydroxyl, aldehyde, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

Plasma treatment process to densify oxide layers

Granted: September 17, 2024
Patent Number: 12094709
Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first…

Plasma enhanced CVD with periodic high voltage bias

Granted: September 17, 2024
Patent Number: 12094707
Embodiments include a method of processing a substrate. In an embodiment, the method comprises flowing one or more source gasses into a processing chamber, and inducing a plasma from the source gases with a plasma source that is operated in a first mode. In an embodiment, the method may further comprise biasing the substrate with a DC power source that is operated in a second mode. In an embodiment, the method may further comprise depositing a film on the substrate.

Single-side stopping and vibration absorbing lamp sleeve and electrodeless lamp illumination device using the same

Granted: September 17, 2024
Patent Number: 12094703
A single-side stopping and vibration absorbing lamp sleeve for fitting with an end part of an electrodeless lamp and being partially disposed in a mounting hole of a metal member includes: a large-diameter part; and a small-diameter part coaxially connected to the large-diameter part, wherein a through hole is formed in the large-diameter part and the small-diameter part, the end part fits with the through hole, an aperture of the through hole ranges between 2.9 mm and 3.1 mm, and an…

Methods and apparatus for controlling ion fraction in physical vapor deposition processes

Granted: September 17, 2024
Patent Number: 12094699
Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the…

Hybrid ion source for aluminum ion generation using a target holder and a solid target

Granted: September 17, 2024
Patent Number: 12094681
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may…

Nanoimprint and etch fabrication of optical devices

Granted: September 17, 2024
Patent Number: 12092956
Methods of forming optical devices using nanoimprint lithography and etch processes are provided. In one embodiment, a method is provided that includes depositing a first resist layer on a substrate, the substrate having a hardmask disposed thereon, imprinting a first resist portion of the first resist layer with a first single-height stamp, etching the first resist portion of the first resist layer, etching a first hardmask portion of the hardmask corresponding to the first resist…

System for illuminating a substrate using an acousto-optic device

Granted: September 17, 2024
Patent Number: 12092941
A method and a system for illuminating a substrate, the system may include an acousto-optic device (AOD); and an etendue expanding optical module. The AOD may include a surface having an illuminated region; wherein the illuminated region is configured to receive a collimated input beam while being fed with a control signal that causes the illuminated region to output illuminated region output beams that are collimated and exhibit deflection angles that scan, during a scan period, a…

High throughput defect detection

Granted: September 17, 2024
Patent Number: 12092584
A method for high throughput defect detection, the method may include (i) performing, using first detection channels, a simultaneous inspection process through a segmented pupil plane that comprises multiple pupil plane segments to select one or more pupil plane segments of interest out of multiple pupil plane segments; (ii) configuring one or more configurable filters related to second detection channels to pass radiation received from the one or more pupil plane segment of interest and…

Method for epitaxially depositing a material on a substrate by flowing a process gas across the substrate from an upper gas inlet to an upper gas outlet and flowing a purge gas from a lower gas inlet to a lower gas outlet

Granted: September 17, 2024
Patent Number: 12091749
Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body,…

Laser dicing glass wafers using advanced laser sources

Granted: September 17, 2024
Patent Number: 12091349
A method and apparatus for substrate dicing are described. The method includes utilizing a laser to dice a substrate along a dicing path to form a perforated line around each device within the substrate. The dicing path is created by exposing the substrate to bursts of laser pulses at different locations around each device. The laser pulses are delivered to the substrate and may have a pulse repetition frequency of greater than about 25 MHz, a pulse width of less than about 15…

Face-up wafer electrochemical planarization apparatus

Granted: September 17, 2024
Patent Number: 12090600
Exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. The apparatuses may include a retaining wall extending from the chuck body. The apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. The apparatuses may include a spindle that is positionable over the chuck body. The apparatuses may include an end effector coupled with a lower end of the spindle. The end effector may…

Determination of substrate layer thickness with polishing pad wear compensation

Granted: September 17, 2024
Patent Number: 12090599
A method of training a neural network includes obtaining two ground truth thickness profiles a test substrate, obtaining two thickness profiles for the test substrate as measured by an in-situ monitoring system while the test substrate is on polishing pads of different thicknesses, generating an estimated thickness profile for another thickness value that is between the two thickness values by interpolating between the two profiles, and training a neural network using the estimated…