In-situ semiconductor processing chamber temperature apparatus
Granted: December 31, 2024
Patent Number:
12183605
Methods and systems for in-situ temperature control are provided. The method includes delivering a temperature-sensing disc into a processing region of a processing chamber without breaking vacuum. The temperature-sensing disc includes one or more cameras configured to perform IR-based imaging. The method further includes measuring a temperature of at least one region of at least one chamber surface in the processing region of the processing chamber by imaging the at least one surface…
High critical temperature metal nitride layer with oxide or oxynitride seed layer
Granted: December 31, 2024
Patent Number:
12185643
A superconducting device includes a substrate, a metal oxide or metal oxynitride seed layer on the substrate, and a metal nitride superconductive layer disposed directly on the seed layer. The seed layer is an oxide or oxynitride of a first metal, and the superconductive layer is a nitride of a different second metal.
Resonator, linear accelerator, and ion implanter having dielectric-free resonator chamber
Granted: December 31, 2024
Patent Number:
12185451
An apparatus may include a resonator chamber, arranged in a vacuum enclosure; an RF electrode assembly, arranged within the vacuum enclosure; and a resonator coil, disposed within the resonator chamber, the resonator coil having a high voltage end, directly connected to at least one RF electrode of the RF electrode assembly.
High-temperature substrate support assembly with failure protection
Granted: December 31, 2024
Patent Number:
12185433
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the…
Threshold voltage modulation for gate-all-around FET architecture
Granted: December 31, 2024
Patent Number:
12183798
A method of forming a gate stack structure includes forming a dipole metal layer on a high-? gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-? gate dielectric layer.
MOSFET gate shielding using an angled implant
Granted: December 31, 2024
Patent Number:
12183794
Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of…
Semiconductor device packaging methods
Granted: December 31, 2024
Patent Number:
12183684
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded dies therein. In certain embodiments, an insulating layer is formed over the…
Methods for copper doped hybrid metallization for line and via
Granted: December 31, 2024
Patent Number:
12183631
Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first…
Multi process air gap formation
Granted: December 31, 2024
Patent Number:
12183627
A method may include providing an array of patterned features on a substrate, the array of patterned features characterized by a spacing. The method may include directing a sputtering species in a first exposure to the array of patterned features, wherein an upper portion of a patterned feature of the array of patterned features forms a protrusion, extending towards an adjacent patterned feature, of the array of patterned features. The method may also include directing a depositing…
Methods and assemblies for gas flow ratio control
Granted: December 31, 2024
Patent Number:
12183606
A master controller identifies a flow ratio setpoint for at least one of a process gas or a carrier gas flow to a process chamber through a set of mass flow controllers. The master controller determines a flow setpoint for the at least one of the process gas or the carrier gas through the set of mass flow controllers based on the identified flow ratio setpoint. The master controller controls the at least one of the process gas flow or the carrier gas flow through each of the set of mass…
Method for forming and patterning a layer and/or substrate
Granted: December 31, 2024
Patent Number:
12183578
In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some…
Gas injection process kit to eliminate arcing and improve uniform gas distribution for a PVD process
Granted: December 31, 2024
Patent Number:
12183560
Embodiments of process shield for use in process chambers are provided herein. In some embodiments, a process shield for use in a process chamber includes: an annular body having an upper portion and a lower portion extending downward and radially inward from the upper portion, wherein the upper portion includes a plurality of annular trenches on an upper surface thereof and having a plurality of slots disposed therebetween to fluidly couple the plurality of annular trenches, wherein one…
Apparatus for temperature control in a substrate processing chamber
Granted: December 31, 2024
Patent Number:
12183559
An adapter for a deposition chamber includes an adapter body extending longitudinally about a central axis between an upper side and lower side opposite the upper side. The adapter body has a central opening about the central axis. The adapter body has a radially outer portion having a connection surface on the lower side and a radially inner portion having a coolant channel and a stepped surface on the lower side. At least a portion of the coolant channel is spaced radially inwardly…
Apparatus and methods for controlling ion energy distribution
Granted: December 31, 2024
Patent Number:
12183557
Embodiments of the present disclosure generally relate to apparatus and methods for controlling an ion energy distribution during plasma processing. In an embodiment, the apparatus includes a substrate support that has a body having a substrate electrode for applying a substrate voltage to a substrate, and an edge ring electrode embedded for applying an edge ring voltage to an edge ring. The apparatus further includes a substrate voltage control circuit coupled to the substrate…
Baffle implementation for improving bottom purge gas flow uniformity
Granted: December 31, 2024
Patent Number:
12183553
The present disclosure generally relates to an apparatus for improving azimuthal uniformity of a pressure profile of a processing gas. In one example, a processing chamber includes a lid, sidewalls, and a substrate support defining a processing volume. A bottom bowl, a chamber base, and a wall define a purge volume. The purge volume is disposed beneath the processing volume. The bottom bowl includes a first surface having a first equalizer hole. A passage couples the processing volume to…
High bandwidth architecture for centralized coherent control at the edge of processing tool
Granted: December 31, 2024
Patent Number:
12183548
Embodiments disclosed herein include a processing tool. In an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.
Method of deep learning-based examination of a semiconductor specimen and system thereof
Granted: December 31, 2024
Patent Number:
12183066
A computerized system and method of training a deep neural network (DNN) is provided. The DNN is trained in a first training cycle using a first training set including first training samples. Each first training sample includes at least one first training image synthetically generated based on design data. Upon receiving a user feedback with respect to the DNN trained using the first training set, a second training cycle is adjusted based on the user feedback by obtaining a second…
Chamber and methods of treating a substrate after exposure to radiation
Granted: December 31, 2024
Patent Number:
12181801
A method and apparatus for performing post-exposure bake operations is described herein. The apparatus includes a plate stack and enables formation of a first high ion density plasma before the ion concentration within the first high ion density plasma is reduced using a diffuser to form a second low ion density plasma. The second low ion density plasma is an electron cloud or a dark plasma. An electric field is formed between a substrate support and the diffuser and through the second…
Nanostructures for optical devices
Granted: December 31, 2024
Patent Number:
12181736
Embodiments of metasurfaces having nanostructures with desired geometric profiles and configurations are provided in the present disclosure. In one embodiment, a metasurface includes a nanostructure formed on a substrate, wherein the nanostructure is cuboidal or cylindrical in shape. In another embodiment, a metasurface includes a plurality of nanostructures on a substrate, wherein each of the nanostructures has a gap greater than 35 nm spaced apart from each other. In yet another…
Gray level ratio inspection
Granted: December 24, 2024
Patent Number:
12175656
A method for gray level ratio inspection comprising: obtaining an electron image that comprises region of interest (ROI) pixels of a ROI of the sample and reference pixels of a reference region of the sample, where the ROI pixels are obtained by illuminating the ROI with the electron beam and the reference pixels are obtained without illuminating the reference region with an electron beam; calculating a reference dark level value based on values of at least some of the reference pixels;…
