METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CONCURRENT MODEL AIDED ELECTRONIC DESIGN AUTOMATION
Granted: July 3, 2008
Application Number:
20080162103
Disclosed are improved methods, systems, and computer program products for predicting performance, manufacturability, and reliability (PMR) using concurrent model analyses for electronic designs. Various embodiments of the present invention disclose a method for predicting PMR with concurrent process model analysis in which a method with concurrent model(s) generate a design for the one or more layers in the electronic circuit. The method then analyzes the impact of the processes or…
Method and system for model-based design and layout of an integrated circuit
Granted: July 3, 2008
Application Number:
20080163134
Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREPARING MULTIPLE LAYERS OF SEMICONDUCTOR SUBSTRATES FOR ELECTRONIC DESIGNS
Granted: July 3, 2008
Application Number:
20080163139
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet…
SUPPLANT DESIGN RULES IN ELECTRONIC DESIGNS
Granted: July 3, 2008
Application Number:
20080163141
Disclosed is an improved method, system, and computer program product for electronic designs with supplant design rules. According to some embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which define absolute or relative threshold(s) for a design feature characteristic. Some other embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which define one…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING THREE-DIMENSIONAL FEATURE CHARACTERISTICS IN ELECTRONIC DESIGNS
Granted: July 3, 2008
Application Number:
20080163142
Disclosed are an improved method, system, and computer program product for a method or system with concurrent models to more accurately determine and represent the three-dimensional design features of electronic designs. Some embodiments disclose a method or a system for determining the design feature characteristics based upon their respective three-dimensional profiles. Some other embodiments further determine whether the design objectives or constraints are met or may be relaxed based…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR TIMING CLOSURE IN ELECTRONIC DESIGNS
Granted: July 3, 2008
Application Number:
20080163148
Disclosed is an improved method, system, and computer program product for timing closure with concurrent models for fabrication, metrology, lithography, and/or imaging processing analyses for electronic designs. Some embodiments of the present invention disclose a method for timing closure with concurrent process model analysis in which a design tool with such concurrent models generates a design for the one or more interconnect levels. The method or system then analyzes the effects of…
Method and System for Model-Based Routing of an Integrated Circuit
Granted: July 3, 2008
Application Number:
20080163150
Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREDICTING THIN FILM INTEGRITY, MANUFACTURABILITY, RELIABILITY, AND PERFORMANCE IN ELECTRONIC DESIGNS
Granted: July 3, 2008
Application Number:
20080160646
Disclosed is an improved method, system, and computer program product for predicting and improving the integrity, manufacturability, reliability, and performance of an electronic circuit feature based on the stresses or strains of design features of electronic designs. Some embodiments identify the design, the concurrent model(s), design feature physical or electrical parameters or attributes, analyzes the stresses or strains to predict the integrity of the design and determines whether…
METHOD AND SYSTEM FOR PROCESS OPTIMIZATION
Granted: June 19, 2008
Application Number:
20080148194
A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.
METHOD AND SYSTEM FOR MASK OPTIMIZATION
Granted: June 19, 2008
Application Number:
20080148216
A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.
Place and Route Tool That Incorporates a Metal-Fill Mechanism
Granted: June 19, 2008
Application Number:
20080148212
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of…
METHOD AND SYSTEM FOR INSPECTION OPTIMIZATION
Granted: June 19, 2008
Application Number:
20080148195
A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.
MODELING AND CROSS CORRELATION OF DESIGN PREDICTED CRITICALITIES FOR OPTIMIZATION OF SEMICONDUCTOR MANUFACTURING
Granted: June 19, 2008
Application Number:
20080147374
A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more…
AUTOMATIC METHOD AND SYSTEM FOR IDENTIFYING AND RECORDING TRANSACTION DATA GENERATED FROM A COMPUTER SIMULATION OF AN INTEGRATED CIRCUIT
Granted: June 19, 2008
Application Number:
20080147372
An automated method and system for managing simulation results of a virtual circuit. Data related to the virtual circuit is accessed. The virtual circuit is subject to a simulation. An initiation of each of one or more transactions occurred during the simulation is identified, and data related to the one or more transactions during the simulation is collected. Upon receipt of a user request, the collected data related to the one or more transactions is output, displayed, stored or made…
PHASE LOCKED LOOP WITH ADAPTIVE PHASE ERROR COMPENSATION
Granted: June 12, 2008
Application Number:
20080136532
An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit…
Method and system for logic design for cell projection particle beam lithography
Granted: June 5, 2008
Application Number:
20080128637
A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing…
FLAT PLACEMENT OF CELLS ON NON-INTEGER MULTIPLE HEIGHT ROWS IN A DIGITAL INTEGRATED CIRCUIT LAYOUT
Granted: June 5, 2008
Application Number:
20080134118
The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and…
Method and system for conducting a low-power design exploration
Granted: May 29, 2008
Application Number:
20080126999
Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the corresponding one or more power requirement files and the RTL netlist, and conducting low-power design explorations using the one or more low-power RTL…
Method and system for equivalence checking of a low power design
Granted: May 29, 2008
Application Number:
20080127014
Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design…
Stencil design and method for cell projection particle beam lithography
Granted: May 22, 2008
Application Number:
20080116397
A method and system for particle beam lithography, such as electron beam (EB) lithography, is disclosed. The method and system include selecting one of a plurality of cell patterns from a stencil mask and partially exposing the cell pattern to a particle beam, such as an electron beam, so as to selectively project a portion of the cell pattern on a substrate.
