SYNTHESIS OF ASSERTIONS FROM STATEMENTS OF POWER INTENT
Granted: April 2, 2009
Application Number:
20090089725
A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low…
Method and System for Mapping Source Elements to Destination Elements as Interconnect Routing Assignments
Granted: April 2, 2009
Application Number:
20090089722
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution.
Method and Apparatus for Implementing Communication Between a Software Side and a Hardware Side of a Test Bench in a Transaction-Based Acceleration Verification System
Granted: March 26, 2009
Application Number:
20090083683
Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are automatically bound to hardware side endpoints of the communication channels during verification based on naming attributes of the transactors and…
METHOD FOR GENERATING OPTIMIZED CONSTRAINT SYSTEMS FOR RETIMABLE DIGITAL DESIGNS
Granted: March 26, 2009
Application Number:
20090083685
A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated…
GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD
Granted: March 19, 2009
Application Number:
20090077505
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The…
GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD
Granted: March 19, 2009
Application Number:
20090077513
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The…
Method and System for Representing Manufacturing and Lithography Information for IC Routing
Granted: March 19, 2009
Application Number:
20090077520
A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
Method and System for Representing Manufacturing and Lithography Information for IC Routing
Granted: March 19, 2009
Application Number:
20090077521
A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS
Granted: March 5, 2009
Application Number:
20090064071
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.
ROBUST DESIGN USING MANUFACTURABILITY MODELS
Granted: January 29, 2009
Application Number:
20090031271
The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.
CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS
Granted: January 29, 2009
Application Number:
20090031261
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
Method and Apparatus for Restructuring a Software Program Hierarchy
Granted: January 8, 2009
Application Number:
20090013315
Method, apparatus, and computer readable medium for restructuring a software program hierarchy having interface files and implementation files that include the interface files are described. In one example, dependencies between program units in the interface files and the implementation files are determined. The dependencies are represented as a plurality of bit strings. Correlated bitstrings of the plurality of bit strings are clustered into a plurality of partitions. Each of the…
METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS
Granted: January 1, 2009
Application Number:
20090007031
Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.
IC TEST VECTOR GENERATOR FOR SYNCHRONIZED PHYSICAL PROBING
Granted: November 20, 2008
Application Number:
20080284453
Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and…
Method and apparatus for controlling power in an emulation system
Granted: October 30, 2008
Application Number:
20080270105
Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a…
Method and apparatus for performing static analysis optimization in a design verification system
Granted: September 25, 2008
Application Number:
20080235640
Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used…
Electronic Design for Integrated Circuits Based on Process Related Variations
Granted: September 4, 2008
Application Number:
20080216027
An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and…
METHOD AND SYSTEM FOR IMPROVEMENT OF DOSE CORRECTION FOR PARTICLE BEAM WRITERS
Granted: August 28, 2008
Application Number:
20080203324
A method and system for dose correction of a particle beam writer is disclosed. The method and system includes reading a file of writing objects that includes dose intensity, calculating a rate of dose intensity change between adjacent writing objects, selecting a writing object that may need accuracy improvement of dose correction based on the rate of dose intensity change, and improving accuracy of the dose correction of the writing object that is selected and its adjacent objects.
Analog/digital partitioning of circuit designs for simulation
Granted: July 31, 2008
Application Number:
20080184181
For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among…
Method and system for conducting design explorations of an integrated circuit
Granted: July 31, 2008
Application Number:
20080184184
Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit.…
