Method and system for improving particle beam lithography
Granted: May 22, 2008
Application Number:
20080116399
A method for particle beam lithography, such as electron beam (EB) lithography, includes forming a plurality of cell patterns on a stencil mask and shaping one or more of the cell patterns with a polygonal-shaped contour. A first polygonal-shaped cell pattern is exposed to a particle beam so as to project the first polygonal-shaped cell pattern on a substrate. A second polygonal-shaped cell pattern, having a contour that mates with the contour of the first polygonal-shaped cell pattern,…
Method and System for Lithography Simulation and Measurement of Critical Dimensions with Improved CD Marker Generation and Placement
Granted: May 22, 2008
Application Number:
20080118852
A method and system for lithography simulation and measurement of critical dimensions with improved CD marker generation and placement is disclosed. The method and system specify a position for measuring a difference between a lithography image and a target pattern, generate one or more CD marker candidates, and select at least one CD marker from the one or more CD marker candidates.
Method and system for lithography simulation and measurement of critical dimensions
Granted: May 22, 2008
Application Number:
20080120073
A method and system for lithography simulation is disclosed. The method and system specify a subject region of a lithography image with a CD marker, specify a threshold intensity over the lithography image, specify a gradient to a threshold value of the threshold intensity, and calculate a sensitivity or ratio of change of an image boundary of the lithography image to lithography process variation.
Library-based solver for modeling an integrated circuit
Granted: May 22, 2008
Application Number:
20080120083
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.
Incremental solver for modeling an integrated circuit
Granted: May 22, 2008
Application Number:
20080120084
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.
Method and system for proximity effect and dose correction for a particle beam writing device
Granted: May 22, 2008
Application Number:
20080116398
A method of particle beam lithography includes selecting at least two cell patterns from a stencil, correcting proximity effect by dose control and by pattern modification for the at least two cell patterns, and writing the at least cell two patterns by one shot of the particle beam after proximity effect correction (PEC).
Method and system for tuning a circuit
Granted: May 1, 2008
Application Number:
20080104548
The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that meets a set of predefined design specifications, and the circuit comprises a group of circuit devices. The method further includes receiving a set of tuning information for the group of circuit…
Integrated sizing, layout, and extractor tool for circuit design
Granted: May 1, 2008
Application Number:
20080104557
Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of design points, where a design point comprises a design of the circuit that meets a set of predefined design specifications, determining sizes for the circuit using a size optimization iteration process, and pausing the sizing optimization iteration process periodically for updating parasitic…
Placer with wires for RF and analog design
Granted: March 27, 2008
Application Number:
20080077898
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the…
Test generation for low power circuits
Granted: March 20, 2008
Application Number:
20080071513
In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual…
AUTO-DETECTING AND DOWNLOADING LICENSED COMPUTER PRODUCTS
Granted: March 13, 2008
Application Number:
20080065551
In a system and method for automatically detecting licensed computer products, a license manager stores contract data indicating a customer and one or more computer products licensed to the customer by a license holder. A customer site is automatically checked for present computer products owned by the license holder. The licensed computer products are compared to the present computer products. In one embodiment, the computer products are software products, but they also may be hardware…
Method and System for Handling Process Related Variations for Integrated Circuits Based Upon Reflections
Granted: January 31, 2008
Application Number:
20080027698
Disclosed is an approach for modeling and correcting for the effects of reflections during lithography processing. Thickness differences across the surfaces in different integrated circuit layers may result in reflectance-related variations. The variations may be modeled and accounted for during the design process for the integrated circuit.
Method and System for Logic Equivalence Checking
Granted: December 20, 2007
Application Number:
20070294649
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
Method and System for Logic Equivalence Checking
Granted: December 20, 2007
Application Number:
20070294650
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
Method and apparatus for synchronizing processors in a hardware emulation system
Granted: December 6, 2007
Application Number:
20070282589
A method, apparatus and method for compiling a hardware design for performing hardware emulation using synchronized processors is described. The apparatus comprises a plurality of processors defining a processor group for evaluating data regarding a hardware design and a synchronizer for synchronizing the operation of the processor group while emulating at least a portion of the hardware design. The method comprises providing a synchronization signal to a plurality of processors defining…
Method and System for Routing
Granted: November 29, 2007
Application Number:
20070277140
Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring…
Predictive Event Scheduling in an Iterative Resolution Network
Granted: November 15, 2007
Application Number:
20070266353
A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive…
Method and System for Context-Specific Mask Writing
Granted: November 15, 2007
Application Number:
20070266364
A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
DUMMY FILL FOR INTEGRATED CIRCUITS
Granted: November 1, 2007
Application Number:
20070256039
Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by other layers in the semiconductor devices. To accomplish this, layers in the design that cannot accommodate dummy fill are modeled to determine their topological variations. Other…
Hardware emulation system having a heterogeneous cluster of processors
Granted: October 11, 2007
Application Number:
20070239422
A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster…
