Cadence Design Systems Patent Applications

Method and System for Context-Specific Mask Inspection

Granted: October 4, 2007
Application Number: 20070233419
A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Method, System, and Article of Manufacture for Implementing Metal-Fill With Power or Ground Connection

Granted: October 4, 2007
Application Number: 20070234265
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of…

Virtual view schematic editor

Granted: October 4, 2007
Application Number: 20070229537
Embodiments of the present invention provide a virtual-view schematic editor for use in CAD systems. In response to a user request, the editor selects elements from a CAD database, determines the connectivity between the elements, and renders the elements on a single display. Virtual views may be created and stored for later re-use within the system.

Hardware emulator having a variable input primitive

Granted: August 23, 2007
Application Number: 20070198241
A hardware emulator having a first primitive for evaluating functions having a first input width and a second primitive, coupled to the first primitive, for evaluating a function having a second input width, where the first input width is unequal to the second input width. The use of either the first primitive or the second primitive is selected depending upon the function to be evaluated.

Method and apparatus for increasing the efficiency of an emulation engine

Granted: August 23, 2007
Application Number: 20070198809
A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the outputs in an output array. The output array allows processors within a cluster to fetch an output from a processor that was written to the output array…

Method and system for improving yield of an integrated circuit

Granted: August 23, 2007
Application Number: 20070198956
Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a…

Method and apparatus for increasing the efficiency of an emulation engine

Granted: August 2, 2007
Application Number: 20070179772
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one…

Frequency-to-current converter

Granted: July 26, 2007
Application Number: 20070172013
A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has…

System and method for generating a plurality of models at different levels of abstraction from a single master model

Granted: July 19, 2007
Application Number: 20070168893
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

System and method for incremental synthesis

Granted: July 5, 2007
Application Number: 20070157131
A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

System and method for verification aware synthesis

Granted: July 5, 2007
Application Number: 20070156378
A method of synthesis of a model representing a design of an integrated circuit is provided including associating a test environment with a first model representing a design of an integrated circuit; translating the first model of the design to a second model of the design; and automatically generating an adaptor that adapts the second model to the test environment.

Calculating intermodulation products and intercept points for circuit distortion analysis

Granted: June 14, 2007
Application Number: 20070136045
A pertubative approach based on the Born approximation resolves weakly nonlinear circuit models without requiring explicit high-order device derivatives. Convergence properties and the relation to Volterra series are discussed. According to the disclosed methods, second and third order intermodulation products (IM2, IM3) and intercept points (IP2, IP3) can be calculated by second and third order Born approximations under weakly nonlinear conditions. A diagrammatic representation of…

System and method pf electron beam writing

Granted: June 7, 2007
Application Number: 20070125967
A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

Analog layout module generator and method

Granted: June 7, 2007
Application Number: 20070130553
In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of…

Method and system for representing analog connectivity in hardware description language designs

Granted: May 31, 2007
Application Number: 20070124706
System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port…

Circuit simulation with decoupled self-heating analysis

Granted: April 5, 2007
Application Number: 20070079205
A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points ti and ti+1 based on predicted electrical responses of the devices at time point ti+1 and as a function of the initial temperatures of the circuit devices at time point ti. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of…

Method and system for validating a hierarchical simulation database

Granted: February 22, 2007
Application Number: 20070044051
System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has…

Modeling a mixed-language mixed-signal design

Granted: November 16, 2006
Application Number: 20060259879
A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining…

Block interstitching using local preferred direction architectures, tools, and apparatus

Granted: November 2, 2006
Application Number: 20060248492
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by implementing a stitching region between the block and external routing structures. The stitching region is implemented using local preferred direction approaches.

Methods of model compilation

Granted: November 2, 2006
Application Number: 20060248518
A method is provided for compiling a model for use in a simulation, the method comprising receiving a description of the model; and automatically converting the description into an implementation of the model that is customized for a selected analysis during simulation.