Method and mechanism for implementing automated PCB routing
Granted: October 26, 2006
Application Number:
20060242614
A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design…
Method and system for performing channel analysis
Granted: September 28, 2006
Application Number:
20060217949
A system, method, computer program and article of manufacture for channel analysis. Channel analysis is a multi gigahertz capacity time domain circuit simulation which uses the impulse response of the channel to determine optimum filter settings and to produce wave form plots in a fraction of the time of circuit simulation.
Transformation of simple subset of PSL into SERE implication formulas for verification with model checking and simulation engines using semantic preserving rewrite rules
Granted: June 22, 2006
Application Number:
20060136879
The disclosure presents a formulation to support simulatable subset (also known as ‘simple-subset’) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the ‘simple-subset’ is transformed to a set of basic formulas. Verification engines are required to support the basic formula only. The basic formula is a form of automata in the property specification language. This is called SERE implication. The efficiency of…
Electrical isomorphism
Granted: May 25, 2006
Application Number:
20060111884
Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the…
System and method for converting a flat netlist into a hierarchical netlist
Granted: May 25, 2006
Application Number:
20060112356
System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each…
Method and system for optimized automated IC package pin routing
Granted: May 25, 2006
Application Number:
20060112366
An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution which can include reassignment of IC nets and/or pin assignments and/or relocation of IC nets.
Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design
Granted: April 6, 2006
Application Number:
20060074626
A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first…
Creating a useful skew for an electronic circuit
Granted: March 23, 2006
Application Number:
20060064658
A method of determining a useful skew for a circuit design includes computing a slack value for each sequential cell in the circuit design, identifying modifiable sequential cells in the circuit design, and computing a target delay for each modifiable sequential cell. One or more sequential cells are discarded based on the slack values. A target slack value for each remaining sequential cell is determined. The remaining cells are sorted based on the target slack values to determine a…
Method and system for performing effective resistance calculation for a network of resistors
Granted: December 29, 2005
Application Number:
20050288914
A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog…
Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
Granted: December 15, 2005
Application Number:
20050278671
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit parameter values. This delay equation calculates the delay for any value in the circuit parameter range. Similar methodology is used to model…
Method and system for context-specific mask writing
Granted: September 29, 2005
Application Number:
20050216877
A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
Granted: July 7, 2005
Application Number:
20050149311
A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, where the primitive database includes a geometries-describing section for storing a plurality of primitive subcircuit blocks; 3) generating an instance database using the geometries-describing section, where the instances…
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
Granted: July 7, 2005
Application Number:
20050149312
A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that has one or more subcircuits. The first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph…
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
Granted: June 30, 2005
Application Number:
20050143966
A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that also has one or more subcircuits. The first branch and second branch are interconnected in the graph through a…
Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit
Granted: April 7, 2005
Application Number:
20050076317
To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer…
Adaptable circuit blocks for use in multi-block chip design
Granted: March 24, 2005
Application Number:
20050066295
Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing…
Method and apparatus for modeling devices having different geometries
Granted: February 3, 2005
Application Number:
20050027501
The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type…
Method for creating patterns for producing integrated circuits
Granted: January 20, 2005
Application Number:
20050015739
To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.
Method and apparatus for representing items in a design layout
Granted: November 11, 2004
Application Number:
20040225983
Some embodiments of the invention provide novel methods for representing items in a design layout. For instance, some embodiments use a method that represents an item in terms of n values that define n half-planes, which when intersected define the shape of the item. In some embodiments, n is a number greater than four. Some embodiments use a method that (1) identifies a first set of location data for the item with respect to a first coordinate system, (2) identifies a second set of…
Method and system for context-specific mask inspection
Granted: July 8, 2004
Application Number:
20040133369
A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
