Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
Granted: July 1, 2004
Application Number:
20040128406
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test…
Method and system for context-specific mask writing
Granted: June 3, 2004
Application Number:
20040107412
A method for generating lithography marks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
Method, system, and article of manufacture for implementing metal-fill on an integrated circuit
Granted: May 20, 2004
Application Number:
20040098393
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of…
Place and route tool that incorporates a metal-fill mechanism
Granted: May 20, 2004
Application Number:
20040098674
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of…
Method, system, and article of manufacture for implementing long wire metal-fill
Granted: May 20, 2004
Application Number:
20040098688
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of…
Adaptive, self-calibrating, low noise output driver
Granted: March 18, 2004
Application Number:
20040051391
An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the first capacitor during a specified interval. The converter includes a feedback loop to adjust the current so as to produce a specified logic level at the specified interval. It is emphasized that this…
Shape based noise tolerance characterization and analysis of LSI
Granted: January 22, 2004
Application Number:
20040015339
The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a…
Method and apparatus for testing multi-port memories
Granted: January 8, 2004
Application Number:
20040006727
A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
Optimization methods for on-chip interconnect geometries suitable for ultra deep sub-micron processes
Granted: December 11, 2003
Application Number:
20030228757
The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted…
Assertion-based transaction recording
Granted: December 4, 2003
Application Number:
20030226124
An assertion based transaction recording method is used to represent a signal-level transaction having a prefix and a suffix as an abstract transaction. The method models the signal-level transaction as an assertion requiring that the transaction suffix must occur following any occurrence of the transaction prefix. A finite-state-machine (FSM) implementation of the assertion records a tentative abstract transaction upon recognizing the first condition of the prefix. If the FSM recognizes…
Variable stage ratio buffer insertion for noise optimization in a logic network
Granted: August 21, 2003
Application Number:
20030159121
A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly…
Hierarchical test circuit structure for chips with multiple circuit blocks
Granted: July 10, 2003
Application Number:
20030131327
A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks…
Topological global routing for automated IC package interconnect
Granted: July 3, 2003
Application Number:
20030126578
An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required…
Assertion handling for timing model extraction
Granted: June 26, 2003
Application Number:
20030120474
Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be…
Programable multi-port memory bist with compact microcode
Granted: June 26, 2003
Application Number:
20030120974
A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are…
Timing model extraction by timing graph reduction
Granted: June 26, 2003
Application Number:
20030121013
Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and…
Block based design methodology
Granted: June 19, 2003
Application Number:
20030115564
A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming…
Bridging apparatus for interconnecting a wireless PAN and a wireless LAN
Granted: December 26, 2002
Application Number:
20020196771
A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11a specification to provide a wireless system level solution for peripheral devices to provide Internet service so interactions. The invention…
Method and system for chip design using remotely located resources
Granted: December 12, 2002
Application Number:
20020188910
A multi-faceted design platform acts as a tool for front-end hardware IC designers who design complex core base System on Chip (SoC). The design platform uses a network such as the Internet to search and gain access to previously designed virtual core blocks. The design platform provides a means to select and transfer all relevant information regarding the selected virtual core blocks and allows the designer to immediately incorporate the virtual core block into the new SoC design. The…
Block based design methodology
Granted: November 7, 2002
Application Number:
20020166098
A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming…
