DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN
Granted: October 18, 2012
Application Number:
20120266110
A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes…
METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR
Granted: October 4, 2012
Application Number:
20120253732
A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and…
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA
Granted: October 4, 2012
Application Number:
20120254818
Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual…
LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD
Granted: September 6, 2012
Application Number:
20120227024
According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the…
METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS
Granted: August 30, 2012
Application Number:
20120221312
The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are…
METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS
Granted: August 30, 2012
Application Number:
20120221988
The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) associated with an electronic circuit design. Embodiments may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the circuit design and generating a three dimensional adaptive mesh model…
METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS
Granted: August 30, 2012
Application Number:
20120221990
The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method…
METHOD AND APPARATUS FOR AMS SIMULATION OF INTEGRATED CIRCUIT DESIGN
Granted: August 2, 2012
Application Number:
20120198405
A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design…
METHOD AND APPARATUS FOR AMS SIMULATION OF INTEGRATED CIRCUIT DESIGN
Granted: August 2, 2012
Application Number:
20120198411
A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design…
System and Method For Providing Compact Mapping Between Dissimilar Memory Systems
Granted: June 21, 2012
Application Number:
20120159113
A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the…
ROBUST DESIGN USING MANUFACTURABILITY MODELS
Granted: June 14, 2012
Application Number:
20120151422
The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.
METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY
Granted: May 24, 2012
Application Number:
20120131524
A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of…
METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES
Granted: April 26, 2012
Application Number:
20120102440
Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.
METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES
Granted: April 19, 2012
Application Number:
20120096414
Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN
Granted: April 12, 2012
Application Number:
20120089954
Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform…
METHOD TO PREVIEW AN UNDO/REDO LIST
Granted: February 23, 2012
Application Number:
20120047434
A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document.
METHOD AND SYSTEM FOR IMPLEMENTING STACKED VIAS
Granted: February 2, 2012
Application Number:
20120030644
The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element.
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS
Granted: January 26, 2012
Application Number:
20120022846
Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the…
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS
Granted: January 26, 2012
Application Number:
20120023467
Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based…
METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS
Granted: January 26, 2012
Application Number:
20120023471
Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ…
