METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS
Granted: January 26, 2012
Application Number:
20120022846
Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the…
METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS
Granted: December 22, 2011
Application Number:
20110314432
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
SYSTEM AND METHOD FOR MANAGEMENT OF CONTROLS IN A GRAPHICAL USER INTERFACE
Granted: November 10, 2011
Application Number:
20110276908
Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within…
METHOD AND SYSTEM FOR IMPLEMENTING CIRCUIT SIMULATORS
Granted: November 3, 2011
Application Number:
20110270556
A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation…
REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL SLACK
Granted: October 13, 2011
Application Number:
20110252389
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be…
INTELLIGENT PATTERN SIGNATURE BASED ON LITHOGRAPHY EFFECTS
Granted: September 29, 2011
Application Number:
20110239168
The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern…
METHOD AND SYSTEM FOR APPROXIMATE PLACEMENT IN ELECTRONIC DESIGNS
Granted: September 29, 2011
Application Number:
20110239177
Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over…
METHOD AND SYSTEM FOR SEARCHING FOR GRAPHICAL OBJECTS OF A DESIGN
Granted: September 8, 2011
Application Number:
20110219320
Searching for graphical objects of a design using a computer system. In one aspect of the inventions, a method includes defining a graphical search pattern based on input received from a user in a graphical interface displayed on a display device, where the search pattern is a graphical object and is defined with a plurality of types of characteristics. The graphical design is searched for all matching instances of graphical objects in the design that match the search pattern and match…
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR INTERACTIVE CHECKING FOR DOUBLE PATTERN LITHOGRAPHY VIOLATIONS
Granted: September 8, 2011
Application Number:
20110219341
Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions…
METHOD AND SYSTEM FOR SEARCHING AND REPLACING GRAPHICAL OBJECTS OF A DESIGN
Granted: September 8, 2011
Application Number:
20110219352
Searching and/or replacing graphical objects of a design using a computer system. In one aspect of the inventions, a method includes searching a graphical design for all matching instances of graphical objects that match a search pattern. A graphical replacement pattern is received and caused to be displayed based on user input, and the matching instances in the graphical design are replaced with the graphical replacement pattern. At least one result of the replacement of the matching…
SYSTEM AND METHOD OF ELECTRON BEAM WRITING
Granted: August 11, 2011
Application Number:
20110192994
A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.
METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTRACTION IN A MULTI-TECHNOLOGY ENVIRONMENT
Granted: July 14, 2011
Application Number:
20110173582
A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.
METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN AN IC DESIGN
Granted: July 7, 2011
Application Number:
20110167400
Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED-SIGNAL VERIFICATION AND LOW POWER SIMULATION
Granted: June 30, 2011
Application Number:
20110161899
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED SIGNAL VERIFICATION AND LOW POWER SIMULATION
Granted: June 30, 2011
Application Number:
20110161900
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more…
METHODS AND SYSTEMS FOR HIGH SIGMA YIELD ESTIMATION
Granted: June 23, 2011
Application Number:
20110153271
For an integrated circuit associated with a plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples, and clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters.…
METHODS AND SYSTEMS FOR HIGH SIGMA YIELD ESTIMATION USING REDUCED DIMENSIONALITY
Granted: June 23, 2011
Application Number:
20110153272
For an integrated circuit associated with a first plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples. A second plurality of parameters is selected that has fewer parameters than the first plurality of parameters. The failed…
METHOD AND SYSTEM FOR OPTIMALLY CONNECTING INTERFACES ACROSS MUTIPLE FABRICS
Granted: June 23, 2011
Application Number:
20110153288
A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each…
METHOD AND SYSTEM FOR SPECIFYING SYSTEM LEVEL CONSTRAINTS IN A CROSS-FABRIC DESIGN ENVIRONMENT
Granted: June 23, 2011
Application Number:
20110153289
A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more…
METHOD AND SYSTEM FOR OPTIMALLY PLACING AND ASSIGNING INTERFACES IN A CROSS-FABRIC DESIGN ENVIRONMENT
Granted: June 23, 2011
Application Number:
20110154276
A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that…
