INTEGRATED CLOCK GATING CELL FOR CIRCUITS WITH DOUBLE EDGE TRIGGERED FLIP-FLOPS
Granted: June 9, 2011
Application Number:
20110133806
A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock…
VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES BASED ON USER ZONE OF FOCUS
Granted: June 2, 2011
Application Number:
20110131525
Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor on the display device. Labels are displayed on the display device, each label associated with a different displayed shape. One or more of the labels are displayed within a zone of focus of eyes of…
VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES
Granted: June 2, 2011
Application Number:
20110131543
Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more…
VISUALIZATION AND INFORMATION DISPLAY FOR SHAPES IN DISPLAYED GRAPHICAL IMAGES BASED ON A CURSOR
Granted: June 2, 2011
Application Number:
20110131544
Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed…
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY SIDEWALL-IMAGE TRANSFER
Granted: May 12, 2011
Application Number:
20110113393
Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer…
SPINE SELECTION MODE FOR LAYOUT EDITING
Granted: April 28, 2011
Application Number:
20110099530
Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a…
METHOD AND SYSTEM FOR MODEL-BASED ROUTING OF AN INTEGRATED CIRCUIT
Granted: April 21, 2011
Application Number:
20110093826
Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.
METHOD AND SYSTEM FOR RE-USING DIGITAL ASSERTIONS IN A MIXED SIGNAL DESIGN
Granted: April 7, 2011
Application Number:
20110083114
A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.
METHOD AND SYSTEM FOR TEST REDUCTION AND ANALYSIS
Granted: March 31, 2011
Application Number:
20110078651
Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller…
MODELING AND SIMULATING DEVICE MISMATCH FOR DESIGNING INTEGRATED CIRCUITS
Granted: March 17, 2011
Application Number:
20110066997
A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.
ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS
Granted: March 17, 2011
Application Number:
20110066995
A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating…
METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS
Granted: March 10, 2011
Application Number:
20110061034
Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREPARING MULTIPLE LAYERS OF SEMICONDUCTOR SUBSTRATES FOR ELECTRONIC DESIGNS
Granted: February 24, 2011
Application Number:
20110046767
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet…
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY DOUBLED PATTERNING
Granted: January 20, 2011
Application Number:
20110014786
Disclosed are a method, apparatus, and program product for routing an electronic design using double patenting that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patenting, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.
ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION
Granted: December 30, 2010
Application Number:
20100333050
For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among…
GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD
Granted: December 23, 2010
Application Number:
20100325597
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The…
METHOD AND SYSTEM PERFORMING RC EXTRACTION
Granted: December 23, 2010
Application Number:
20100325595
A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to…
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING HOTSPOT DETECTION, REPAIR, AND OPTIMIZATION OF AN ELECTRONIC CIRCUIT DESIGN
Granted: December 23, 2010
Application Number:
20100324878
Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction…
IC TEST VECTOR GENERATOR FOR SYNCHRONIZED PHYSICAL PROBING
Granted: December 23, 2010
Application Number:
20100321055
Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and…
METHOD AND SYSTEM FOR VIEWING AND EDITING AN IMAGE IN A MAGNIFIED VIEW
Granted: November 11, 2010
Application Number:
20100287493
Viewing and editing of a displayed image in a magnified view. In one aspect, a method for displaying a magnified image using a computer system includes causing a display on a display device of a first image, and causing a display on the display device of a second image that is a portion of the first image. The second image has a zoomed-in view that is a closer view of the portion than in the first image. At least one edit is caused to the second image in response to at least one input…
