Methods, Systems, and Computer-Program Products for Item Selection and Positioning Suitable for High-Altitude and Context Sensitive Editing of Electrical Circuits
Granted: August 12, 2010
Application Number:
20100205575
Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are…
ADAPTIVE MESH RESOLUTION IN ELECTRIC CIRCUIT SIMULATION AND ANALYSIS
Granted: August 12, 2010
Application Number:
20100205572
An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and…
Method and System for Implementing Graphical Analysis of Hierarchical Coverage Information Using Treemaps
Granted: July 1, 2010
Application Number:
20100169853
An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach…
METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND USER INTERFACE FOR PERFORMING POWER INFERENCE
Granted: June 24, 2010
Application Number:
20100161303
An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to…
METHOD AND SYSTEM PERFORMING BLOCK-LEVEL RC EXTRACTION
Granted: June 24, 2010
Application Number:
20100162188
A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as…
SYSTEM AND METHOD FOR SYNTHESIS REUSE
Granted: June 24, 2010
Application Number:
20100162189
A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.
METHOD AND SYSTEM FOR PERFORMING CELL MODELING AND SELECTION
Granted: June 24, 2010
Application Number:
20100162191
An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based…
Contention-Free Level Converting Flip-Flops for Low-Swing Clocking
Granted: June 17, 2010
Application Number:
20100148836
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop…
Method and System for Implementing a User Interface with Ghosting
Granted: June 17, 2010
Application Number:
20100153888
An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the…
Method and System for Performing Software Verification
Granted: June 17, 2010
Application Number:
20100153924
Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a tightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from…
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING INTERACTIVE CROSS-DOMAIN PACKAGE DRIVEN I/O PLANNING AND PLACEMENT OPTIMIZATION
Granted: May 20, 2010
Application Number:
20100125822
Disclosed are a method, a system, and a computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization of an electronic circuit design. In some embodiments, the method identifies an object on a first EDA tool session, determines a drop location for the first object based on a tentative location in the first EDA tool session, places the first object at the drop location, and adjusts the drop location via a second EDA tool session,…
METHOD AND SYSTEM FOR CONDUCTING DESIGN EXPLORATIONS OF AN INTEGRATED CIRCUIT
Granted: May 13, 2010
Application Number:
20100122228
Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit.…
METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS
Granted: May 6, 2010
Application Number:
20100115207
An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to…
OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMING INFORMATION
Granted: May 6, 2010
Application Number:
20100115477
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be…
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN
Granted: May 6, 2010
Application Number:
20100115478
Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform…
METHOD AND SYSTEM FOR SCHEMATIC-VISUALIZATION DRIVEN TOPOLOGICALLY-EQUIVALENT LAYOUT DESIGN IN RFSiP
Granted: May 6, 2010
Application Number:
20100115487
An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.
METHODS, SYSTEM, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING COMPACT MANUFACTURING MODEL IN ELECTRONIC DESIGN AUTOMATION
Granted: April 1, 2010
Application Number:
20100083200
Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the…
Analysis of Physical Systems via Model Libraries Thereof
Granted: March 18, 2010
Application Number:
20100070934
A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and used to determine a corresponding characteristic of the physical system without repeating the numerical solution method originally used to create the model. Instead, a mapping may…
Achieving Clock Timing Closure in Designing an Integrated Circuit
Granted: March 18, 2010
Application Number:
20100070941
Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing…
TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS
Granted: March 4, 2010
Application Number:
20100058129
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.
