METHOD AND SYSTEM FOR ROUTING
Granted: February 25, 2010
Application Number:
20100050146
Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring…
METHOD AND SYSTEM FOR ROUTING
Granted: February 25, 2010
Application Number:
20100050143
Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring…
MANAGEMENT OF VERY LARGE STREAMING DATA SETS FOR EFFICIENT WRITES AND READS TO AND FROM PERSISTENT STORAGE
Granted: February 25, 2010
Application Number:
20100049935
A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING INCREMENTAL PLACEMENT IN ELECTRONICS DESIGN
Granted: February 11, 2010
Application Number:
20100037196
Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing the perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, the abstract flow is computed, the target locations of various electronic components to be placed are identified, the relative ordering of electronic components are…
Context-Aware Non-Linear Graphic Editing
Granted: February 11, 2010
Application Number:
20100037136
A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and…
SPINE SELECTION MODE FOR LAYOUT EDITING
Granted: January 7, 2010
Application Number:
20100004902
Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a…
TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS
Granted: December 31, 2009
Application Number:
20090326854
A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The…
METHOD AND SYSTEM FOR TESTING AND ANALYZING USER INTERFACES
Granted: December 24, 2009
Application Number:
20090320002
A system and method is described in which the state of the art in automated software applications is significantly improved. According to some approaches, interface testing is implemented and based upon a verification language and a verification environment. The system and method support the concepts of constrained random test generation, coverage, constrained random generation, and dynamic checks.
METHOD AND SYSTEM PERFORMING CIRCUIT DESIGN PREDICTIONS
Granted: December 24, 2009
Application Number:
20090319976
Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).
PEAK POWER DETECTION IN DIGITAL DESIGNS USING EMULATION SYSTEMS
Granted: October 29, 2009
Application Number:
20090271167
A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining…
PARAMETRIC PERTURBATIONS OF PERFORMANCE METRICS FOR INTEGRATED CIRCUITS
Granted: September 10, 2009
Application Number:
20090228250
A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition; and saving one or more values for the parametric perturbations in a computer-readable medium. Calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values…
METHOD AND APPARATUS FOR SIMULATING QUASI-PERIODIC CIRCUIT OPERATING CONDITIONS USING A MIXED FREQUENCY/TIME ALGORITHM
Granted: August 20, 2009
Application Number:
20090210202
Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of…
Method And Apparatus For Processing Assertions In Assertion-Based Verification of A Logic Design
Granted: August 13, 2009
Application Number:
20090204931
Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The…
Method for Accounting for Process Variation in the Design of Integrated Circuits
Granted: August 6, 2009
Application Number:
20090199145
A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.
METHOD AND SYSTEM FOR IMPLEMENTING TIMING ANALYSIS AND OPTIMIZATION OF AN ELECTRONIC DESIGN BASED UPON EXTENDED REGIONS OF ANALYSIS
Granted: July 2, 2009
Application Number:
20090172619
Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically…
METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS
Granted: July 2, 2009
Application Number:
20090172623
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
Method and System for Implementing Stacked Vias
Granted: July 2, 2009
Application Number:
20090172624
The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element.
METHOD AND SYSTEM FOR VISUAL IMPLEMENTATION OF LAYOUT STRUCTURES FOR AN INTEGRATED CIRCUIT
Granted: July 2, 2009
Application Number:
20090172626
The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual presentation could be employed to display layout choices during the initial design entry phase for the electronic design.
Method and System for Utilizing Hard and Preferred Rules for C-Routing of Electronic Designs
Granted: July 2, 2009
Application Number:
20090172628
An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.
Method, System, and Computer Program Product for Implementing External Domain Independent Modeling Framework in a System Design
Granted: July 2, 2009
Application Number:
20090172632
Disclosed are a method, system, and computer program product for implementing external domain independent modeling framework in a system design. In some embodiments, the method or system comprises importing an external model in an external format into the framework while substantially preserving some or all of the interpretation of the external model, determining a internal common representation for the external model within the framework, and displaying or storing the internal common…
